diff options
| author | Michael Hennerich <michael.hennerich@analog.com> | 2009-02-04 16:49:45 +0800 |
|---|---|---|
| committer | Bryan Wu <cooloney@kernel.org> | 2009-02-04 16:49:45 +0800 |
| commit | 331693129d1764e38b15561e5712347fd591b2a9 (patch) | |
| tree | 7114d0bd0f8149f0e5ed041a91942a4d712e2d27 /arch/blackfin/include | |
| parent | 41245ac5952e5b05e6fbb7c188eae0947f640189 (diff) | |
Blackfin arch: Fix Bug - Kernel does not boot if re-program clocks
On BF561 EBIU_SDGCTL bit 31 controls the SDRAM external data
path width, typically set 0 for a 32-bit bus width. On other
Blackfin derivatives this bit should be set by default.
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
Signed-off-by: Bryan Wu <cooloney@kernel.org>
Diffstat (limited to 'arch/blackfin/include')
| -rw-r--r-- | arch/blackfin/include/asm/mem_init.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/blackfin/include/asm/mem_init.h b/arch/blackfin/include/asm/mem_init.h index 255a9316ad3..61f7487fbf1 100644 --- a/arch/blackfin/include/asm/mem_init.h +++ b/arch/blackfin/include/asm/mem_init.h @@ -115,7 +115,7 @@ #define mem_SDRRC (((CONFIG_SCLK_HZ / 1000) * SDRAM_Tref) / SDRAM_NRA) - (SDRAM_tRAS_num + SDRAM_tRP_num) /* Enable SCLK Out */ -#define mem_SDGCTL (0x80000000 | SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP | SDRAM_tRCD | SDRAM_tWR | PSS) +#define mem_SDGCTL (SCTLE | SDRAM_CL | SDRAM_tRAS | SDRAM_tRP | SDRAM_tRCD | SDRAM_tWR | PSS) #else #define mem_SDRRC CONFIG_MEM_SDRRC #define mem_SDGCTL CONFIG_MEM_SDGCTL |