diff options
author | Michael Hennerich <michael.hennerich@analog.com> | 2007-06-21 11:34:16 +0800 |
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committer | Bryan Wu <bryan.wu@analog.com> | 2007-06-21 11:34:16 +0800 |
commit | 1c5d2265a82f8d3fa0471a60ca98072b3c53c299 (patch) | |
tree | d0644427e9d700df594fa8dbcbb1338bfd982ac2 /arch/blackfin/mach-common/ints-priority-sc.c | |
parent | f8ffe652a01506e85e2dd579c58e50a3ba391921 (diff) |
Blackfin arch: add missing implementations SIC_IWR crosses several registers
SIC_IWR crosses several registers
- add missing implementations
- make sure SIC_IWR is SET after boot
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Diffstat (limited to 'arch/blackfin/mach-common/ints-priority-sc.c')
-rw-r--r-- | arch/blackfin/mach-common/ints-priority-sc.c | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/arch/blackfin/mach-common/ints-priority-sc.c b/arch/blackfin/mach-common/ints-priority-sc.c index cec0f841fb5..27838da55d6 100644 --- a/arch/blackfin/mach-common/ints-priority-sc.c +++ b/arch/blackfin/mach-common/ints-priority-sc.c @@ -472,8 +472,12 @@ int __init init_arch_irq(void) bfin_write_SIC_IMASK0(SIC_UNMASK_ALL); bfin_write_SIC_IMASK1(SIC_UNMASK_ALL); bfin_write_SIC_IMASK2(SIC_UNMASK_ALL); + bfin_write_SIC_IWR0(IWR_ENABLE_ALL); + bfin_write_SIC_IWR1(IWR_ENABLE_ALL); + bfin_write_SIC_IWR2(IWR_ENABLE_ALL); #else bfin_write_SIC_IMASK(SIC_UNMASK_ALL); + bfin_write_SIC_IWR(IWR_ENABLE_ALL); #endif SSYNC(); |