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authorYi Li <yi.li@analog.com>2009-12-04 06:56:21 +0000
committerMike Frysinger <vapier@gentoo.org>2010-03-09 00:30:45 -0500
commitc9784ebb23be1e2ef23f537d6df04e0ea0206802 (patch)
treefd0eb67c23deb8f1073c9162bd105d8b0d9e3962 /arch/blackfin/mach-common/smp.c
parent3630ac34b0ab346ff0910401dbed7af624be7027 (diff)
Blackfin: flush caches on SMP when one core calls another via IPI
Sometimes a SMP system will randomly panic at boot. This is due to caches being out of sync when one core tries to signal the other. So when one core calls another via IPI, flush the data caches. Signed-off-by: Yi Li <yi.li@analog.com> Signed-off-by: Mike Frysinger <vapier@gentoo.org>
Diffstat (limited to 'arch/blackfin/mach-common/smp.c')
-rw-r--r--arch/blackfin/mach-common/smp.c26
1 files changed, 24 insertions, 2 deletions
diff --git a/arch/blackfin/mach-common/smp.c b/arch/blackfin/mach-common/smp.c
index 369e687582b..eddb720c718 100644
--- a/arch/blackfin/mach-common/smp.c
+++ b/arch/blackfin/mach-common/smp.c
@@ -122,9 +122,17 @@ static void ipi_call_function(unsigned int cpu, struct ipi_message *msg)
wait = msg->call_struct.wait;
cpu_clear(cpu, msg->call_struct.pending);
func(info);
- if (wait)
+ if (wait) {
+#ifdef __ARCH_SYNC_CORE_DCACHE
+ /*
+ * 'wait' usually means synchronization between CPUs.
+ * Invalidate D cache in case shared data was changed
+ * by func() to ensure cache coherence.
+ */
+ resync_core_dcache();
+#endif
cpu_clear(cpu, msg->call_struct.waitmask);
- else
+ } else
kfree(msg);
}
@@ -219,6 +227,13 @@ int smp_call_function(void (*func)(void *info), void *info, int wait)
blackfin_dcache_invalidate_range(
(unsigned long)(&msg->call_struct.waitmask),
(unsigned long)(&msg->call_struct.waitmask));
+#ifdef __ARCH_SYNC_CORE_DCACHE
+ /*
+ * Invalidate D cache in case shared data was changed by
+ * other processors to ensure cache coherence.
+ */
+ resync_core_dcache();
+#endif
kfree(msg);
}
return 0;
@@ -261,6 +276,13 @@ int smp_call_function_single(int cpuid, void (*func) (void *info), void *info,
blackfin_dcache_invalidate_range(
(unsigned long)(&msg->call_struct.waitmask),
(unsigned long)(&msg->call_struct.waitmask));
+#ifdef __ARCH_SYNC_CORE_DCACHE
+ /*
+ * Invalidate D cache in case shared data was changed by
+ * other processors to ensure cache coherence.
+ */
+ resync_core_dcache();
+#endif
kfree(msg);
}
return 0;