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authorMike Frysinger <michael.frysinger@analog.com>2007-07-24 15:58:41 +0800
committerBryan Wu <bryan.wu@analog.com>2007-07-24 15:58:41 +0800
commit315a8e34f7c12609947f9b435faae451aaa5dd41 (patch)
treeb2fae7b2a6b1753c84834d24bcabb955f58a58c0 /arch/blackfin
parentf695baf2df9e0413d3521661070103711545207a (diff)
Blackfin arch: setup aliases for some core Core A MMRs
setup aliases for some core Core A MMRs to ease porting in cases where common code would actually want Core A (or Core B MMR is reserved) Signed-off-by: Mike Frysinger <michael.frysinger@analog.com> Signed-off-by: Bryan Wu <bryan.wu@analog.com>
Diffstat (limited to 'arch/blackfin')
-rw-r--r--arch/blackfin/mach-bf561/head.S10
1 files changed, 5 insertions, 5 deletions
diff --git a/arch/blackfin/mach-bf561/head.S b/arch/blackfin/mach-bf561/head.S
index 2f08bcb2dde..38650a62898 100644
--- a/arch/blackfin/mach-bf561/head.S
+++ b/arch/blackfin/mach-bf561/head.S
@@ -440,15 +440,15 @@ ENTRY(_bfin_reset)
SSYNC;
/* make sure SYSCR is set to use BMODE */
- P0.h = hi(SICA_SYSCR);
- P0.l = lo(SICA_SYSCR);
- R0.l = 0x20;
+ P0.h = hi(SYSCR);
+ P0.l = lo(SYSCR);
+ R0.l = 0x20; /* on BF561, disable core b */
W[P0] = R0.l;
SSYNC;
/* issue a system soft reset */
- P1.h = hi(SICA_SWRST);
- P1.l = lo(SICA_SWRST);
+ P1.h = hi(SWRST);
+ P1.l = lo(SWRST);
R1.l = 0x0007;
W[P1] = R1;
SSYNC;