diff options
| author | Paul Mackerras <paulus@samba.org> | 2008-01-24 10:07:21 +1100 |
|---|---|---|
| committer | Paul Mackerras <paulus@samba.org> | 2008-01-24 10:07:21 +1100 |
| commit | 9156ad48338e0306e508ead5c0d9986050744475 (patch) | |
| tree | 37f3a90e38190052ecf3cdf9171dfdddd37b56fd /arch/ia64 | |
| parent | fa28237cfcc5827553044cbd6ee52e33692b0faa (diff) | |
| parent | 8f7b3d156d348b6766833cd4e272d0d19b501e64 (diff) | |
Merge branch 'linux-2.6'
Diffstat (limited to 'arch/ia64')
| -rw-r--r-- | arch/ia64/kernel/unaligned.c | 11 | ||||
| -rw-r--r-- | arch/ia64/sn/kernel/xp_nofault.S | 10 |
2 files changed, 14 insertions, 7 deletions
diff --git a/arch/ia64/kernel/unaligned.c b/arch/ia64/kernel/unaligned.c index 2173de9fe91..f6a1aeb742b 100644 --- a/arch/ia64/kernel/unaligned.c +++ b/arch/ia64/kernel/unaligned.c @@ -1488,16 +1488,19 @@ ia64_handle_unaligned (unsigned long ifa, struct pt_regs *regs) case LDFA_OP: case LDFCCLR_OP: case LDFCNC_OP: - case LDF_IMM_OP: - case LDFA_IMM_OP: - case LDFCCLR_IMM_OP: - case LDFCNC_IMM_OP: if (u.insn.x) ret = emulate_load_floatpair(ifa, u.insn, regs); else ret = emulate_load_float(ifa, u.insn, regs); break; + case LDF_IMM_OP: + case LDFA_IMM_OP: + case LDFCCLR_IMM_OP: + case LDFCNC_IMM_OP: + ret = emulate_load_float(ifa, u.insn, regs); + break; + case STF_OP: case STF_IMM_OP: ret = emulate_store_float(ifa, u.insn, regs); diff --git a/arch/ia64/sn/kernel/xp_nofault.S b/arch/ia64/sn/kernel/xp_nofault.S index 54e8973b6e9..98e7c7dbfdd 100644 --- a/arch/ia64/sn/kernel/xp_nofault.S +++ b/arch/ia64/sn/kernel/xp_nofault.S @@ -3,7 +3,7 @@ * License. See the file "COPYING" in the main directory of this archive * for more details. * - * Copyright (c) 2004-2005 Silicon Graphics, Inc. All Rights Reserved. + * Copyright (c) 2004-2007 Silicon Graphics, Inc. All Rights Reserved. */ @@ -14,6 +14,11 @@ * PIO read fails, the MCA handler will force the error to look * corrected and vector to the xp_error_PIOR which will return an error. * + * The definition of "consumption" and the time it takes for an MCA + * to surface is processor implementation specific. This code + * is sufficient on Itanium through the Montvale processor family. + * It may need to be adjusted for future processor implementations. + * * extern int xp_nofault_PIOR(void *remote_register); */ @@ -22,11 +27,10 @@ xp_nofault_PIOR: mov r8=r0 // Stage a success return value ld8.acq r9=[r32];; // PIO Read the specified register adds r9=1,r9;; // Add to force consumption - or r9=r9,r9;; // Or to force consumption + srlz.i;; // Allow time for MCA to surface br.ret.sptk.many b0;; // Return success .global xp_error_PIOR xp_error_PIOR: mov r8=1 // Return value of 1 br.ret.sptk.many b0;; // Return failure - |