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authorLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 15:20:36 -0700
committerLinus Torvalds <torvalds@ppc970.osdl.org>2005-04-16 15:20:36 -0700
commit1da177e4c3f41524e886b7f1b8a0c1fc7321cac2 (patch)
tree0bba044c4ce775e45a88a51686b5d9f90697ea9d /arch/mips/au1000/common
Linux-2.6.12-rc2
Initial git repository build. I'm not bothering with the full history, even though we have it. We can create a separate "historical" git archive of that later if we want to, and in the meantime it's about 3.2GB when imported into git - space that would just make the early git days unnecessarily complicated, when we don't have a lot of good infrastructure for it. Let it rip!
Diffstat (limited to 'arch/mips/au1000/common')
-rw-r--r--arch/mips/au1000/common/Makefile15
-rw-r--r--arch/mips/au1000/common/au1xxx_irqmap.c224
-rw-r--r--arch/mips/au1000/common/clocks.c96
-rw-r--r--arch/mips/au1000/common/cputable.c55
-rw-r--r--arch/mips/au1000/common/dbdma.c836
-rw-r--r--arch/mips/au1000/common/dbg_io.c122
-rw-r--r--arch/mips/au1000/common/dma.c243
-rw-r--r--arch/mips/au1000/common/int-handler.S68
-rw-r--r--arch/mips/au1000/common/irq.c654
-rw-r--r--arch/mips/au1000/common/pci.c97
-rw-r--r--arch/mips/au1000/common/platform.c53
-rw-r--r--arch/mips/au1000/common/power.c493
-rw-r--r--arch/mips/au1000/common/prom.c162
-rw-r--r--arch/mips/au1000/common/puts.c145
-rw-r--r--arch/mips/au1000/common/reset.c195
-rw-r--r--arch/mips/au1000/common/setup.c195
-rw-r--r--arch/mips/au1000/common/sleeper.S149
-rw-r--r--arch/mips/au1000/common/time.c469
-rw-r--r--arch/mips/au1000/common/usbdev.c1557
19 files changed, 5828 insertions, 0 deletions
diff --git a/arch/mips/au1000/common/Makefile b/arch/mips/au1000/common/Makefile
new file mode 100644
index 00000000000..594b75e5e08
--- /dev/null
+++ b/arch/mips/au1000/common/Makefile
@@ -0,0 +1,15 @@
+#
+# Copyright 2000 MontaVista Software Inc.
+# Author: MontaVista Software, Inc.
+# ppopov@mvista.com or source@mvista.com
+#
+# Makefile for the Alchemy Au1000 CPU, generic files.
+#
+
+obj-y += prom.o int-handler.o irq.o puts.o time.o reset.o \
+ au1xxx_irqmap.o clocks.o platform.o power.o setup.o \
+ sleeper.o cputable.o dma.o dbdma.o
+
+obj-$(CONFIG_AU1X00_USB_DEVICE) += usbdev.o
+obj-$(CONFIG_KGDB) += dbg_io.o
+obj-$(CONFIG_PCI) += pci.o
diff --git a/arch/mips/au1000/common/au1xxx_irqmap.c b/arch/mips/au1000/common/au1xxx_irqmap.c
new file mode 100644
index 00000000000..8a0f39f67c5
--- /dev/null
+++ b/arch/mips/au1000/common/au1xxx_irqmap.c
@@ -0,0 +1,224 @@
+/*
+ * BRIEF MODULE DESCRIPTION
+ * Au1xxx processor specific IRQ tables
+ *
+ * Copyright 2004 Embedded Edge, LLC
+ * dan@embeddededge.com
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#include <linux/config.h>
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/irq.h>
+#include <linux/kernel_stat.h>
+#include <linux/module.h>
+#include <linux/signal.h>
+#include <linux/sched.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/timex.h>
+#include <linux/slab.h>
+#include <linux/random.h>
+#include <linux/delay.h>
+#include <linux/bitops.h>
+
+#include <asm/bootinfo.h>
+#include <asm/io.h>
+#include <asm/mipsregs.h>
+#include <asm/system.h>
+#include <asm/mach-au1x00/au1000.h>
+
+/* The IC0 interrupt table. This is processor, rather than
+ * board dependent, so no reason to keep this info in the board
+ * dependent files.
+ *
+ * Careful if you change match 2 request!
+ * The interrupt handler is called directly from the low level dispatch code.
+ */
+au1xxx_irq_map_t au1xxx_ic0_map[] = {
+
+#if defined(CONFIG_SOC_AU1000)
+ { AU1000_UART0_INT, INTC_INT_HIGH_LEVEL, 0},
+ { AU1000_UART1_INT, INTC_INT_HIGH_LEVEL, 0},
+ { AU1000_UART2_INT, INTC_INT_HIGH_LEVEL, 0},
+ { AU1000_UART3_INT, INTC_INT_HIGH_LEVEL, 0},
+ { AU1000_SSI0_INT, INTC_INT_HIGH_LEVEL, 0},
+ { AU1000_SSI1_INT, INTC_INT_HIGH_LEVEL, 0},
+ { AU1000_DMA_INT_BASE, INTC_INT_HIGH_LEVEL, 0},
+ { AU1000_DMA_INT_BASE+1, INTC_INT_HIGH_LEVEL, 0},
+ { AU1000_DMA_INT_BASE+2, INTC_INT_HIGH_LEVEL, 0},
+ { AU1000_DMA_INT_BASE+3, INTC_INT_HIGH_LEVEL, 0},
+ { AU1000_DMA_INT_BASE+4, INTC_INT_HIGH_LEVEL, 0},
+ { AU1000_DMA_INT_BASE+5, INTC_INT_HIGH_LEVEL, 0},
+ { AU1000_DMA_INT_BASE+6, INTC_INT_HIGH_LEVEL, 0},
+ { AU1000_DMA_INT_BASE+7, INTC_INT_HIGH_LEVEL, 0},
+ { AU1000_TOY_INT, INTC_INT_RISE_EDGE, 0 },
+ { AU1000_TOY_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },
+ { AU1000_TOY_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },
+ { AU1000_TOY_MATCH2_INT, INTC_INT_RISE_EDGE, 1 },
+ { AU1000_RTC_INT, INTC_INT_RISE_EDGE, 0 },
+ { AU1000_RTC_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },
+ { AU1000_RTC_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },
+ { AU1000_RTC_MATCH2_INT, INTC_INT_RISE_EDGE, 0 },
+ { AU1000_IRDA_TX_INT, INTC_INT_HIGH_LEVEL, 0},
+ { AU1000_IRDA_RX_INT, INTC_INT_HIGH_LEVEL, 0},
+ { AU1000_USB_DEV_REQ_INT, INTC_INT_HIGH_LEVEL, 0 },
+ { AU1000_USB_DEV_SUS_INT, INTC_INT_RISE_EDGE, 0 },
+ { AU1000_USB_HOST_INT, INTC_INT_LOW_LEVEL, 0 },
+ { AU1000_ACSYNC_INT, INTC_INT_RISE_EDGE, 0 },
+ { AU1000_MAC0_DMA_INT, INTC_INT_HIGH_LEVEL, 0},
+ { AU1000_MAC1_DMA_INT, INTC_INT_HIGH_LEVEL, 0},
+ { AU1000_AC97C_INT, INTC_INT_RISE_EDGE, 0 },
+
+#elif defined(CONFIG_SOC_AU1500)
+
+ { AU1500_UART0_INT, INTC_INT_HIGH_LEVEL, 0},
+ { AU1000_PCI_INTA, INTC_INT_LOW_LEVEL, 0 },
+ { AU1000_PCI_INTB, INTC_INT_LOW_LEVEL, 0 },
+ { AU1500_UART3_INT, INTC_INT_HIGH_LEVEL, 0},
+ { AU1000_PCI_INTC, INTC_INT_LOW_LEVEL, 0 },
+ { AU1000_PCI_INTD, INTC_INT_LOW_LEVEL, 0 },
+ { AU1000_DMA_INT_BASE, INTC_INT_HIGH_LEVEL, 0},
+ { AU1000_DMA_INT_BASE+1, INTC_INT_HIGH_LEVEL, 0},
+ { AU1000_DMA_INT_BASE+2, INTC_INT_HIGH_LEVEL, 0},
+ { AU1000_DMA_INT_BASE+3, INTC_INT_HIGH_LEVEL, 0},
+ { AU1000_DMA_INT_BASE+4, INTC_INT_HIGH_LEVEL, 0},
+ { AU1000_DMA_INT_BASE+5, INTC_INT_HIGH_LEVEL, 0},
+ { AU1000_DMA_INT_BASE+6, INTC_INT_HIGH_LEVEL, 0},
+ { AU1000_DMA_INT_BASE+7, INTC_INT_HIGH_LEVEL, 0},
+ { AU1000_TOY_INT, INTC_INT_RISE_EDGE, 0 },
+ { AU1000_TOY_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },
+ { AU1000_TOY_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },
+ { AU1000_TOY_MATCH2_INT, INTC_INT_RISE_EDGE, 1 },
+ { AU1000_RTC_INT, INTC_INT_RISE_EDGE, 0 },
+ { AU1000_RTC_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },
+ { AU1000_RTC_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },
+ { AU1000_RTC_MATCH2_INT, INTC_INT_RISE_EDGE, 0 },
+ { AU1000_USB_DEV_REQ_INT, INTC_INT_HIGH_LEVEL, 0 },
+ { AU1000_USB_DEV_SUS_INT, INTC_INT_RISE_EDGE, 0 },
+ { AU1000_USB_HOST_INT, INTC_INT_LOW_LEVEL, 0 },
+ { AU1000_ACSYNC_INT, INTC_INT_RISE_EDGE, 0 },
+ { AU1500_MAC0_DMA_INT, INTC_INT_HIGH_LEVEL, 0},
+ { AU1500_MAC1_DMA_INT, INTC_INT_HIGH_LEVEL, 0},
+ { AU1000_AC97C_INT, INTC_INT_RISE_EDGE, 0 },
+
+#elif defined(CONFIG_SOC_AU1100)
+
+ { AU1100_UART0_INT, INTC_INT_HIGH_LEVEL, 0},
+ { AU1100_UART1_INT, INTC_INT_HIGH_LEVEL, 0},
+ { AU1100_SD_INT, INTC_INT_HIGH_LEVEL, 0},
+ { AU1100_UART3_INT, INTC_INT_HIGH_LEVEL, 0},
+ { AU1000_SSI0_INT, INTC_INT_HIGH_LEVEL, 0},
+ { AU1000_SSI1_INT, INTC_INT_HIGH_LEVEL, 0},
+ { AU1000_DMA_INT_BASE, INTC_INT_HIGH_LEVEL, 0},
+ { AU1000_DMA_INT_BASE+1, INTC_INT_HIGH_LEVEL, 0},
+ { AU1000_DMA_INT_BASE+2, INTC_INT_HIGH_LEVEL, 0},
+ { AU1000_DMA_INT_BASE+3, INTC_INT_HIGH_LEVEL, 0},
+ { AU1000_DMA_INT_BASE+4, INTC_INT_HIGH_LEVEL, 0},
+ { AU1000_DMA_INT_BASE+5, INTC_INT_HIGH_LEVEL, 0},
+ { AU1000_DMA_INT_BASE+6, INTC_INT_HIGH_LEVEL, 0},
+ { AU1000_DMA_INT_BASE+7, INTC_INT_HIGH_LEVEL, 0},
+ { AU1000_TOY_INT, INTC_INT_RISE_EDGE, 0 },
+ { AU1000_TOY_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },
+ { AU1000_TOY_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },
+ { AU1000_TOY_MATCH2_INT, INTC_INT_RISE_EDGE, 1 },
+ { AU1000_RTC_INT, INTC_INT_RISE_EDGE, 0 },
+ { AU1000_RTC_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },
+ { AU1000_RTC_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },
+ { AU1000_RTC_MATCH2_INT, INTC_INT_RISE_EDGE, 0 },
+ { AU1000_IRDA_TX_INT, INTC_INT_HIGH_LEVEL, 0},
+ { AU1000_IRDA_RX_INT, INTC_INT_HIGH_LEVEL, 0},
+ { AU1000_USB_DEV_REQ_INT, INTC_INT_HIGH_LEVEL, 0 },
+ { AU1000_USB_DEV_SUS_INT, INTC_INT_RISE_EDGE, 0 },
+ { AU1000_USB_HOST_INT, INTC_INT_LOW_LEVEL, 0 },
+ { AU1000_ACSYNC_INT, INTC_INT_RISE_EDGE, 0 },
+ { AU1100_MAC0_DMA_INT, INTC_INT_HIGH_LEVEL, 0},
+ /*{ AU1000_GPIO215_208_INT, INTC_INT_HIGH_LEVEL, 0},*/
+ { AU1100_LCD_INT, INTC_INT_HIGH_LEVEL, 0},
+ { AU1000_AC97C_INT, INTC_INT_RISE_EDGE, 0 },
+
+#elif defined(CONFIG_SOC_AU1550)
+
+ { AU1550_UART0_INT, INTC_INT_HIGH_LEVEL, 0},
+ { AU1550_PCI_INTA, INTC_INT_LOW_LEVEL, 0 },
+ { AU1550_PCI_INTB, INTC_INT_LOW_LEVEL, 0 },
+ { AU1550_DDMA_INT, INTC_INT_HIGH_LEVEL, 0},
+ { AU1550_CRYPTO_INT, INTC_INT_HIGH_LEVEL, 0},
+ { AU1550_PCI_INTC, INTC_INT_LOW_LEVEL, 0 },
+ { AU1550_PCI_INTD, INTC_INT_LOW_LEVEL, 0 },
+ { AU1550_PCI_RST_INT, INTC_INT_LOW_LEVEL, 0 },
+ { AU1550_UART1_INT, INTC_INT_HIGH_LEVEL, 0},
+ { AU1550_UART3_INT, INTC_INT_HIGH_LEVEL, 0},
+ { AU1550_PSC0_INT, INTC_INT_HIGH_LEVEL, 0},
+ { AU1550_PSC1_INT, INTC_INT_HIGH_LEVEL, 0},
+ { AU1550_PSC2_INT, INTC_INT_HIGH_LEVEL, 0},
+ { AU1550_PSC3_INT, INTC_INT_HIGH_LEVEL, 0},
+ { AU1550_TOY_INT, INTC_INT_RISE_EDGE, 0 },
+ { AU1550_TOY_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },
+ { AU1550_TOY_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },
+ { AU1550_TOY_MATCH2_INT, INTC_INT_RISE_EDGE, 1 },
+ { AU1550_RTC_INT, INTC_INT_RISE_EDGE, 0 },
+ { AU1550_RTC_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },
+ { AU1550_RTC_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },
+ { AU1550_RTC_MATCH2_INT, INTC_INT_RISE_EDGE, 0 },
+ { AU1550_NAND_INT, INTC_INT_RISE_EDGE, 0},
+ { AU1550_USB_DEV_REQ_INT, INTC_INT_HIGH_LEVEL, 0 },
+ { AU1550_USB_DEV_SUS_INT, INTC_INT_RISE_EDGE, 0 },
+ { AU1550_USB_HOST_INT, INTC_INT_LOW_LEVEL, 0 },
+ { AU1550_MAC0_DMA_INT, INTC_INT_HIGH_LEVEL, 0},
+ { AU1550_MAC1_DMA_INT, INTC_INT_HIGH_LEVEL, 0},
+
+#elif defined(CONFIG_SOC_AU1200)
+
+ { AU1200_UART0_INT, INTC_INT_HIGH_LEVEL, 0},
+ { AU1200_SWT_INT, INTC_INT_RISE_EDGE, 0 },
+ { AU1200_SD_INT, INTC_INT_HIGH_LEVEL, 0},
+ { AU1200_DDMA_INT, INTC_INT_HIGH_LEVEL, 0},
+ { AU1200_MAE_BE_INT, INTC_INT_HIGH_LEVEL, 0 },
+ { AU1200_UART1_INT, INTC_INT_HIGH_LEVEL, 0},
+ { AU1200_MAE_FE_INT, INTC_INT_HIGH_LEVEL, 0 },
+ { AU1200_PSC0_INT, INTC_INT_HIGH_LEVEL, 0},
+ { AU1200_PSC1_INT, INTC_INT_HIGH_LEVEL, 0},
+ { AU1200_AES_INT, INTC_INT_HIGH_LEVEL, 0},
+ { AU1200_CAMERA_INT, INTC_INT_HIGH_LEVEL, 0},
+ { AU1200_TOY_INT, INTC_INT_RISE_EDGE, 0 },
+ { AU1200_TOY_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },
+ { AU1200_TOY_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },
+ { AU1200_TOY_MATCH2_INT, INTC_INT_RISE_EDGE, 1 },
+ { AU1200_RTC_INT, INTC_INT_RISE_EDGE, 0 },
+ { AU1200_RTC_MATCH0_INT, INTC_INT_RISE_EDGE, 0 },
+ { AU1200_RTC_MATCH1_INT, INTC_INT_RISE_EDGE, 0 },
+ { AU1200_RTC_MATCH2_INT, INTC_INT_RISE_EDGE, 0 },
+ { AU1200_NAND_INT, INTC_INT_RISE_EDGE, 0},
+ { AU1200_USB_INT, INTC_INT_HIGH_LEVEL, 0 },
+ { AU1200_LCD_INT, INTC_INT_HIGH_LEVEL, 0},
+ { AU1200_MAE_BOTH_INT, INTC_INT_HIGH_LEVEL, 0},
+
+#else
+#error "Error: Unknown Alchemy SOC"
+#endif
+
+};
+
+int au1xxx_ic0_nr_irqs = sizeof(au1xxx_ic0_map)/sizeof(au1xxx_irq_map_t);
+
diff --git a/arch/mips/au1000/common/clocks.c b/arch/mips/au1000/common/clocks.c
new file mode 100644
index 00000000000..3ce6cace0eb
--- /dev/null
+++ b/arch/mips/au1000/common/clocks.c
@@ -0,0 +1,96 @@
+/*
+ * BRIEF MODULE DESCRIPTION
+ * Simple Au1000 clocks routines.
+ *
+ * Copyright 2001 MontaVista Software Inc.
+ * Author: MontaVista Software, Inc.
+ * ppopov@mvista.com or source@mvista.com
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <linux/module.h>
+#include <asm/mach-au1x00/au1000.h>
+
+static unsigned int au1x00_clock; // Hz
+static unsigned int lcd_clock; // KHz
+static unsigned long uart_baud_base;
+
+/*
+ * Set the au1000_clock
+ */
+void set_au1x00_speed(unsigned int new_freq)
+{
+ au1x00_clock = new_freq;
+}
+
+unsigned int get_au1x00_speed(void)
+{
+ return au1x00_clock;
+}
+
+
+
+/*
+ * The UART baud base is not known at compile time ... if
+ * we want to be able to use the same code on different
+ * speed CPUs.
+ */
+unsigned long get_au1x00_uart_baud_base(void)
+{
+ return uart_baud_base;
+}
+
+void set_au1x00_uart_baud_base(unsigned long new_baud_base)
+{
+ uart_baud_base = new_baud_base;
+}
+
+/*
+ * Calculate the Au1x00's LCD clock based on the current
+ * cpu clock and the system bus clock, and try to keep it
+ * below 40 MHz (the Pb1000 board can lock-up if the LCD
+ * clock is over 40 MHz).
+ */
+void set_au1x00_lcd_clock(void)
+{
+ unsigned int static_cfg0;
+ unsigned int sys_busclk =
+ (get_au1x00_speed()/1000) /
+ ((int)(au_readl(SYS_POWERCTRL)&0x03) + 2);
+
+ static_cfg0 = au_readl(MEM_STCFG0);
+
+ if (static_cfg0 & (1<<11))
+ lcd_clock = sys_busclk / 5; /* note: BCLK switching fails with D5 */
+ else
+ lcd_clock = sys_busclk / 4;
+
+ if (lcd_clock > 50000) /* Epson MAX */
+ printk("warning: LCD clock too high (%d KHz)\n", lcd_clock);
+}
+
+unsigned int get_au1x00_lcd_clock(void)
+{
+ return lcd_clock;
+}
+
+EXPORT_SYMBOL(get_au1x00_lcd_clock);
diff --git a/arch/mips/au1000/common/cputable.c b/arch/mips/au1000/common/cputable.c
new file mode 100644
index 00000000000..f5521dfccfd
--- /dev/null
+++ b/arch/mips/au1000/common/cputable.c
@@ -0,0 +1,55 @@
+/*
+ * arch/mips/au1000/common/cputable.c
+ *
+ * Copyright (C) 2004 Dan Malek (dan@embeddededge.com)
+ * Copied from PowerPC and updated for Alchemy Au1xxx processors.
+ *
+ * Copyright (C) 2001 Ben. Herrenschmidt (benh@kernel.crashing.org)
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ */
+#include <linux/string.h>
+#include <linux/sched.h>
+#include <linux/threads.h>
+#include <linux/init.h>
+#include <asm/mach-au1x00/au1000.h>
+
+struct cpu_spec* cur_cpu_spec[NR_CPUS];
+
+/* With some thought, we can probably use the mask to reduce the
+ * size of the table.
+ */
+struct cpu_spec cpu_specs[] = {
+ { 0xffffffff, 0x00030100, "Au1000 DA", 1, 0 },
+ { 0xffffffff, 0x00030201, "Au1000 HA", 1, 0 },
+ { 0xffffffff, 0x00030202, "Au1000 HB", 1, 0 },
+ { 0xffffffff, 0x00030203, "Au1000 HC", 1, 1 },
+ { 0xffffffff, 0x00030204, "Au1000 HD", 1, 1 },
+ { 0xffffffff, 0x01030200, "Au1500 AB", 1, 1 },
+ { 0xffffffff, 0x01030201, "Au1500 AC", 0, 1 },
+ { 0xffffffff, 0x01030202, "Au1500 AD", 0, 1 },
+ { 0xffffffff, 0x02030200, "Au1100 AB", 1, 1 },
+ { 0xffffffff, 0x02030201, "Au1100 BA", 1, 1 },
+ { 0xffffffff, 0x02030202, "Au1100 BC", 1, 1 },
+ { 0xffffffff, 0x02030203, "Au1100 BD", 0, 1 },
+ { 0xffffffff, 0x02030204, "Au1100 BE", 0, 1 },
+ { 0xffffffff, 0x03030200, "Au1550 AA", 0, 1 },
+ { 0xffffffff, 0x04030200, "Au1200 AA", 0, 1 },
+ { 0x00000000, 0x00000000, "Unknown Au1xxx", 1, 0 },
+};
+
+void
+set_cpuspec(void)
+{
+ struct cpu_spec *sp;
+ u32 prid;
+
+ prid = read_c0_prid();
+ sp = cpu_specs;
+ while ((prid & sp->prid_mask) != sp->prid_value)
+ sp++;
+ cur_cpu_spec[0] = sp;
+}
diff --git a/arch/mips/au1000/common/dbdma.c b/arch/mips/au1000/common/dbdma.c
new file mode 100644
index 00000000000..adfc3172aac
--- /dev/null
+++ b/arch/mips/au1000/common/dbdma.c
@@ -0,0 +1,836 @@
+/*
+ *
+ * BRIEF MODULE DESCRIPTION
+ * The Descriptor Based DMA channel manager that first appeared
+ * on the Au1550. I started with dma.c, but I think all that is
+ * left is this initial comment :-)
+ *
+ * Copyright 2004 Embedded Edge, LLC
+ * dan@embeddededge.com
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+#include <linux/config.h>
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/sched.h>
+#include <linux/slab.h>
+#include <linux/spinlock.h>
+#include <linux/string.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <asm/mach-au1x00/au1000.h>
+#include <asm/mach-au1x00/au1xxx_dbdma.h>
+#include <asm/system.h>
+
+#if defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200)
+
+/*
+ * The Descriptor Based DMA supports up to 16 channels.
+ *
+ * There are 32 devices defined. We keep an internal structure
+ * of devices using these channels, along with additional
+ * information.
+ *
+ * We allocate the descriptors and allow access to them through various
+ * functions. The drivers allocate the data buffers and assign them
+ * to the descriptors.
+ */
+static DEFINE_SPINLOCK(au1xxx_dbdma_spin_lock);
+
+/* I couldn't find a macro that did this......
+*/
+#define ALIGN_ADDR(x, a) ((((u32)(x)) + (a-1)) & ~(a-1))
+
+static volatile dbdma_global_t *dbdma_gptr = (dbdma_global_t *)DDMA_GLOBAL_BASE;
+static int dbdma_initialized;
+static void au1xxx_dbdma_init(void);
+
+typedef struct dbdma_device_table {
+ u32 dev_id;
+ u32 dev_flags;
+ u32 dev_tsize;
+ u32 dev_devwidth;
+ u32 dev_physaddr; /* If FIFO */
+ u32 dev_intlevel;
+ u32 dev_intpolarity;
+} dbdev_tab_t;
+
+typedef struct dbdma_chan_config {
+ u32 chan_flags;
+ u32 chan_index;
+ dbdev_tab_t *chan_src;
+ dbdev_tab_t *chan_dest;
+ au1x_dma_chan_t *chan_ptr;
+ au1x_ddma_desc_t *chan_desc_base;
+ au1x_ddma_desc_t *get_ptr, *put_ptr, *cur_ptr;
+ void *chan_callparam;
+ void (*chan_callback)(int, void *, struct pt_regs *);
+} chan_tab_t;
+
+#define DEV_FLAGS_INUSE (1 << 0)
+#define DEV_FLAGS_ANYUSE (1 << 1)
+#define DEV_FLAGS_OUT (1 << 2)
+#define DEV_FLAGS_IN (1 << 3)
+
+static dbdev_tab_t dbdev_tab[] = {
+#ifdef CONFIG_SOC_AU1550
+ /* UARTS */
+ { DSCR_CMD0_UART0_TX, DEV_FLAGS_OUT, 0, 8, 0x11100004, 0, 0 },
+ { DSCR_CMD0_UART0_RX, DEV_FLAGS_IN, 0, 8, 0x11100000, 0, 0 },
+ { DSCR_CMD0_UART3_TX, DEV_FLAGS_OUT, 0, 8, 0x11400004, 0, 0 },
+ { DSCR_CMD0_UART3_RX, DEV_FLAGS_IN, 0, 8, 0x11400000, 0, 0 },
+
+ /* EXT DMA */
+ { DSCR_CMD0_DMA_REQ0, 0, 0, 0, 0x00000000, 0, 0 },
+ { DSCR_CMD0_DMA_REQ1, 0, 0, 0, 0x00000000, 0, 0 },
+ { DSCR_CMD0_DMA_REQ2, 0, 0, 0, 0x00000000, 0, 0 },
+ { DSCR_CMD0_DMA_REQ3, 0, 0, 0, 0x00000000, 0, 0 },
+
+ /* USB DEV */
+ { DSCR_CMD0_USBDEV_RX0, DEV_FLAGS_IN, 4, 8, 0x10200000, 0, 0 },
+ { DSCR_CMD0_USBDEV_TX0, DEV_FLAGS_OUT, 4, 8, 0x10200004, 0, 0 },
+ { DSCR_CMD0_USBDEV_TX1, DEV_FLAGS_OUT, 4, 8, 0x10200008, 0, 0 },
+ { DSCR_CMD0_USBDEV_TX2, DEV_FLAGS_OUT, 4, 8, 0x1020000c, 0, 0 },
+ { DSCR_CMD0_USBDEV_RX3, DEV_FLAGS_IN, 4, 8, 0x10200010, 0, 0 },
+ { DSCR_CMD0_USBDEV_RX4, DEV_FLAGS_IN, 4, 8, 0x10200014, 0, 0 },
+
+ /* PSC 0 */
+ { DSCR_CMD0_PSC0_TX, DEV_FLAGS_OUT, 0, 0, 0x11a0001c, 0, 0 },
+ { DSCR_CMD0_PSC0_RX, DEV_FLAGS_IN, 0, 0, 0x11a0001c, 0, 0 },
+
+ /* PSC 1 */
+ { DSCR_CMD0_PSC1_TX, DEV_FLAGS_OUT, 0, 0, 0x11b0001c, 0, 0 },
+ { DSCR_CMD0_PSC1_RX, DEV_FLAGS_IN, 0, 0, 0x11b0001c, 0, 0 },
+
+ /* PSC 2 */
+ { DSCR_CMD0_PSC2_TX, DEV_FLAGS_OUT, 0, 0, 0x10a0001c, 0, 0 },
+ { DSCR_CMD0_PSC2_RX, DEV_FLAGS_IN, 0, 0, 0x10a0001c, 0, 0 },
+
+ /* PSC 3 */
+ { DSCR_CMD0_PSC3_TX, DEV_FLAGS_OUT, 0, 0, 0x10b0001c, 0, 0 },
+ { DSCR_CMD0_PSC3_RX, DEV_FLAGS_IN, 0, 0, 0x10b0001c, 0, 0 },
+
+ { DSCR_CMD0_PCI_WRITE, 0, 0, 0, 0x00000000, 0, 0 }, /* PCI */
+ { DSCR_CMD0_NAND_FLASH, 0, 0, 0, 0x00000000, 0, 0 }, /* NAND */
+
+ /* MAC 0 */
+ { DSCR_CMD0_MAC0_RX, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
+ { DSCR_CMD0_MAC0_TX, DEV_FLAGS_OUT, 0, 0, 0x00000000, 0, 0 },
+
+ /* MAC 1 */
+ { DSCR_CMD0_MAC1_RX, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
+ { DSCR_CMD0_MAC1_TX, DEV_FLAGS_OUT, 0, 0, 0x00000000, 0, 0 },
+
+#endif /* CONFIG_SOC_AU1550 */
+
+#ifdef CONFIG_SOC_AU1200
+ { DSCR_CMD0_UART0_TX, DEV_FLAGS_OUT, 0, 8, 0x11100004, 0, 0 },
+ { DSCR_CMD0_UART0_RX, DEV_FLAGS_IN, 0, 8, 0x11100000, 0, 0 },
+ { DSCR_CMD0_UART1_TX, DEV_FLAGS_OUT, 0, 8, 0x11200004, 0, 0 },
+ { DSCR_CMD0_UART1_RX, DEV_FLAGS_IN, 0, 8, 0x11200000, 0, 0 },
+
+ { DSCR_CMD0_DMA_REQ0, 0, 0, 0, 0x00000000, 0, 0 },
+ { DSCR_CMD0_DMA_REQ1, 0, 0, 0, 0x00000000, 0, 0 },
+
+ { DSCR_CMD0_MAE_BE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
+ { DSCR_CMD0_MAE_FE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
+ { DSCR_CMD0_MAE_BOTH, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
+ { DSCR_CMD0_LCD, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
+
+ { DSCR_CMD0_SDMS_TX0, DEV_FLAGS_OUT, 0, 0, 0x00000000, 0, 0 },
+ { DSCR_CMD0_SDMS_RX0, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
+ { DSCR_CMD0_SDMS_TX1, DEV_FLAGS_OUT, 0, 0, 0x00000000, 0, 0 },
+ { DSCR_CMD0_SDMS_RX1, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
+
+ { DSCR_CMD0_AES_TX, DEV_FLAGS_OUT, 0, 0, 0x00000000, 0, 0 },
+ { DSCR_CMD0_AES_RX, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
+
+ { DSCR_CMD0_PSC0_TX, DEV_FLAGS_OUT, 0, 0, 0x11a0001c, 0, 0 },
+ { DSCR_CMD0_PSC0_RX, DEV_FLAGS_IN, 0, 0, 0x11a0001c, 0, 0 },
+ { DSCR_CMD0_PSC0_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
+
+ { DSCR_CMD0_PSC1_TX, DEV_FLAGS_OUT, 0, 0, 0x11b0001c, 0, 0 },
+ { DSCR_CMD0_PSC1_RX, DEV_FLAGS_IN, 0, 0, 0x11b0001c, 0, 0 },
+ { DSCR_CMD0_PSC1_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
+
+ { DSCR_CMD0_CIM_RXA, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
+ { DSCR_CMD0_CIM_RXB, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
+ { DSCR_CMD0_CIM_RXC, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
+ { DSCR_CMD0_CIM_SYNC, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
+
+ { DSCR_CMD0_NAND_FLASH, DEV_FLAGS_IN, 0, 0, 0x00000000, 0, 0 },
+
+#endif // CONFIG_SOC_AU1200
+
+ { DSCR_CMD0_THROTTLE, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
+ { DSCR_CMD0_ALWAYS, DEV_FLAGS_ANYUSE, 0, 0, 0x00000000, 0, 0 },
+};
+
+#define DBDEV_TAB_SIZE (sizeof(dbdev_tab) / sizeof(dbdev_tab_t))
+
+static chan_tab_t *chan_tab_ptr[NUM_DBDMA_CHANS];
+
+static dbdev_tab_t *
+find_dbdev_id (u32 id)
+{
+ int i;
+ dbdev_tab_t *p;
+ for (i = 0; i < DBDEV_TAB_SIZE; ++i) {
+ p = &dbdev_tab[i];
+ if (p->dev_id == id)
+ return p;
+ }
+ return NULL;
+}
+
+/* Allocate a channel and return a non-zero descriptor if successful.
+*/
+u32
+au1xxx_dbdma_chan_alloc(u32 srcid, u32 destid,
+ void (*callback)(int, void *, struct pt_regs *), void *callparam)
+{
+ unsigned long flags;
+ u32 used, chan, rv;
+ u32 dcp;
+ int i;
+ dbdev_tab_t *stp, *dtp;
+ chan_tab_t *ctp;
+ volatile au1x_dma_chan_t *cp;
+
+ /* We do the intialization on the first channel allocation.
+ * We have to wait because of the interrupt handler initialization
+ * which can't be done successfully during board set up.
+ */
+ if (!dbdma_initialized)
+ au1xxx_dbdma_init();
+ dbdma_initialized = 1;
+
+ if ((srcid > DSCR_NDEV_IDS) || (destid > DSCR_NDEV_IDS))
+ return 0;
+
+ if ((stp = find_dbdev_id(srcid)) == NULL) return 0;
+ if ((dtp = find_dbdev_id(destid)) == NULL) return 0;
+
+ used = 0;
+ rv = 0;
+
+ /* Check to see if we can get both channels.
+ */
+ spin_lock_irqsave(&au1xxx_dbdma_spin_lock, flags);
+ if (!(stp->dev_flags & DEV_FLAGS_INUSE) ||
+ (stp->dev_flags & DEV_FLAGS_ANYUSE)) {
+ /* Got source */
+ stp->dev_flags |= DEV_FLAGS_INUSE;
+ if (!(dtp->dev_flags & DEV_FLAGS_INUSE) ||
+ (dtp->dev_flags & DEV_FLAGS_ANYUSE)) {
+ /* Got destination */
+ dtp->dev_flags |= DEV_FLAGS_INUSE;
+ }
+ else {
+ /* Can't get dest. Release src.
+ */
+ stp->dev_flags &= ~DEV_FLAGS_INUSE;
+ used++;
+ }
+ }
+ else {
+ used++;
+ }
+ spin_unlock_irqrestore(&au1xxx_dbdma_spin_lock, flags);
+
+ if (!used) {
+ /* Let's see if we can allocate a channel for it.
+ */
+ ctp = NULL;
+ chan = 0;
+ spin_lock_irqsave(&au1xxx_dbdma_spin_lock, flags);
+ for (i=0; i<NUM_DBDMA_CHANS; i++) {
+ if (chan_tab_ptr[i] == NULL) {
+ /* If kmalloc fails, it is caught below same
+ * as a channel not available.
+ */
+ ctp = kmalloc(sizeof(chan_tab_t), GFP_KERNEL);
+ chan_tab_ptr[i] = ctp;
+ ctp->chan_index = chan = i;
+ break;
+ }
+ }
+ spin_unlock_irqrestore(&au1xxx_dbdma_spin_lock, flags);
+
+ if (ctp != NULL) {
+ memset(ctp, 0, sizeof(chan_tab_t));
+ dcp = DDMA_CHANNEL_BASE;
+ dcp += (0x0100 * chan);
+ ctp->chan_ptr = (au1x_dma_chan_t *)dcp;
+ cp = (volatile au1x_dma_chan_t *)dcp;
+ ctp->chan_src = stp;
+ ctp->chan_dest = dtp;
+ ctp->chan_callback = callback;
+ ctp->chan_callparam = callparam;
+
+ /* Initialize channel configuration.
+ */
+ i = 0;
+ if (stp->dev_intlevel)
+ i |= DDMA_CFG_SED;
+ if (stp->dev_intpolarity)
+ i |= DDMA_CFG_SP;
+ if (dtp->dev_intlevel)
+ i |= DDMA_CFG_DED;
+ if (dtp->dev_intpolarity)
+ i |= DDMA_CFG_DP;
+ cp->ddma_cfg = i;
+ au_sync();
+
+ /* Return a non-zero value that can be used to
+ * find the channel information in subsequent
+ * operations.
+ */
+ rv = (u32)(&chan_tab_ptr[chan]);
+ }
+ else {
+ /* Release devices.
+ */
+ stp->dev_flags &= ~DEV_FLAGS_INUSE;
+ dtp->dev_flags &= ~DEV_FLAGS_INUSE;
+ }
+ }
+ return rv;
+}
+
+/* Set the device width if source or destination is a FIFO.
+ * Should be 8, 16, or 32 bits.
+ */
+u32
+au1xxx_dbdma_set_devwidth(u32 chanid, int bits)
+{
+ u32 rv;
+ chan_tab_t *ctp;
+ dbdev_tab_t *stp, *dtp;
+
+ ctp = *((chan_tab_t **)chanid);
+ stp = ctp->chan_src;
+ dtp = ctp->chan_dest;
+ rv = 0;
+
+ if (stp->dev_flags & DEV_FLAGS_IN) { /* Source in fifo */
+ rv = stp->dev_devwidth;
+ stp->dev_devwidth = bits;
+ }
+ if (dtp->dev_flags & DEV_FLAGS_OUT) { /* Destination out fifo */
+ rv = dtp->dev_devwidth;
+ dtp->dev_devwidth = bits;
+ }
+
+ return rv;
+}
+
+/* Allocate a descriptor ring, initializing as much as possible.
+*/
+u32
+au1xxx_dbdma_ring_alloc(u32 chanid, int entries)
+{
+ int i;
+ u32 desc_base, srcid, destid;
+ u32 cmd0, cmd1, src1, dest1;
+ u32 src0, dest0;
+ chan_tab_t *ctp;
+ dbdev_tab_t *stp, *dtp;
+ au1x_ddma_desc_t *dp;
+
+ /* I guess we could check this to be within the
+ * range of the table......
+ */
+ ctp = *((chan_tab_t **)chanid);
+ stp = ctp->chan_src;
+ dtp = ctp->chan_dest;
+
+ /* The descriptors must be 32-byte aligned. There is a
+ * possibility the allocation will give us such an address,
+ * and if we try that first we are likely to not waste larger
+ * slabs of memory.
+ */
+ desc_base = (u32)kmalloc(entries * sizeof(au1x_ddma_desc_t), GFP_KERNEL);
+ if (desc_base == 0)
+ return 0;
+
+ if (desc_base & 0x1f) {
+ /* Lost....do it again, allocate extra, and round
+ * the address base.
+ */
+ kfree((const void *)desc_base);
+ i = entries * sizeof(au1x_ddma_desc_t);
+ i += (sizeof(au1x_ddma_desc_t) - 1);
+ if ((desc_base = (u32)kmalloc(i, GFP_KERNEL)) == 0)
+ return 0;
+
+ desc_base = ALIGN_ADDR(desc_base, sizeof(au1x_ddma_desc_t));
+ }
+ dp = (au1x_ddma_desc_t *)desc_base;
+
+ /* Keep track of the base descriptor.
+ */
+ ctp->chan_desc_base = dp;
+
+ /* Initialize the rings with as much information as we know.
+ */
+ srcid = stp->dev_id;
+ destid = dtp->dev_id;
+
+ cmd0 = cmd1 = src1 = dest1 = 0;
+ src0 = dest0 = 0;
+
+ cmd0 |= DSCR_CMD0_SID(srcid);
+ cmd0 |= DSCR_CMD0_DID(destid);
+ cmd0 |= DSCR_CMD0_IE | DSCR_CMD0_CV;
+ cmd0 |= DSCR_CMD0_ST(DSCR_CMD0_ST_CURRENT);
+
+ switch (stp->dev_devwidth) {
+ case 8:
+ cmd0 |= DSCR_CMD0_SW(DSCR_CMD0_BYTE);
+ break;
+ case 16:
+ cmd0 |= DSCR_CMD0_SW(DSCR_CMD0_HALFWORD);
+ break;
+ case 32:
+ default:
+ cmd0 |= DSCR_CMD0_SW(DSCR_CMD0_WORD);
+ break;
+ }
+
+ switch (dtp->dev_devwidth) {
+ case 8:
+ cmd0 |= DSCR_CMD0_DW(DSCR_CMD0_BYTE);
+ break;
+ case 16:
+ cmd0 |= DSCR_CMD0_DW(DSCR_CMD0_HALFWORD);
+ break;
+ case 32:
+ default:
+ cmd0 |= DSCR_CMD0_DW(DSCR_CMD0_WORD);
+ break;
+ }
+
+ /* If the device is marked as an in/out FIFO, ensure it is
+ * set non-coherent.
+ */
+ if (stp->dev_flags & DEV_FLAGS_IN)
+ cmd0 |= DSCR_CMD0_SN; /* Source in fifo */
+ if (dtp->dev_flags & DEV_FLAGS_OUT)
+ cmd0 |= DSCR_CMD0_DN; /* Destination out fifo */
+
+ /* Set up source1. For now, assume no stride and increment.
+ * A channel attribute update can change this later.
+ */
+ switch (stp->dev_tsize) {
+ case 1:
+ src1 |= DSCR_SRC1_STS(DSCR_xTS_SIZE1);
+ break;
+ case 2:
+ src1 |= DSCR_SRC1_STS(DSCR_xTS_SIZE2);
+ break;
+ case 4:
+ src1 |= DSCR_SRC1_STS(DSCR_xTS_SIZE4);
+ break;
+ case 8:
+ default:
+ src1 |= DSCR_SRC1_STS(DSCR_xTS_SIZE8);
+ break;
+ }
+
+ /* If source input is fifo, set static address.
+ */
+ if (stp->dev_flags & DEV_FLAGS_IN) {
+ src0 = stp->dev_physaddr;
+ src1 |= DSCR_SRC1_SAM(DSCR_xAM_STATIC);
+ }
+
+ /* Set up dest1. For now, assume no stride and increment.
+ * A channel attribute update can change this later.
+ */
+ switch (dtp->dev_tsize) {
+ case 1:
+ dest1 |= DSCR_DEST1_DTS(DSCR_xTS_SIZE1);
+ break;
+ case 2:
+ dest1 |= DSCR_DEST1_DTS(DSCR_xTS_SIZE2);
+ break;
+ case 4:
+ dest1 |= DSCR_DEST1_DTS(DSCR_xTS_SIZE4);
+ break;
+ case 8:
+ default:
+ dest1 |= DSCR_DEST1_DTS(DSCR_xTS_SIZE8);
+ break;
+ }
+
+ /* If destination output is fifo, set static address.
+ */
+ if (dtp->dev_flags & DEV_FLAGS_OUT) {
+ dest0 = dtp->dev_physaddr;
+ dest1 |= DSCR_DEST1_DAM(DSCR_xAM_STATIC);
+ }
+
+ for (i=0; i<entries; i++) {
+ dp->dscr_cmd0 = cmd0;
+ dp->dscr_cmd1 = cmd1;
+ dp->dscr_source0 = src0;
+ dp->dscr_source1 = src1;
+ dp->dscr_dest0 = dest0;
+ dp->dscr_dest1 = dest1;
+ dp->dscr_stat = 0;
+ dp->dscr_nxtptr = DSCR_NXTPTR(virt_to_phys(dp + 1));
+ dp++;
+ }
+
+ /* Make last descrptor point to the first.
+ */
+ dp--;
+ dp->dscr_nxtptr = DSCR_NXTPTR(virt_to_phys(ctp->chan_desc_base));
+ ctp->get_ptr = ctp->put_ptr = ctp->cur_ptr = ctp->chan_desc_base;
+
+ return (u32)(ctp->chan_desc_base);
+}
+
+/* Put a source buffer into the DMA ring.
+ * This updates the source pointer and byte count. Normally used
+ * for memory to fifo transfers.
+ */
+u32
+au1xxx_dbdma_put_source(u32 chanid, void *buf, int nbytes)
+{
+ chan_tab_t *ctp;
+ au1x_ddma_desc_t *dp;
+
+ /* I guess we could check this to be within the
+ * range of the table......
+ */
+ ctp = *((chan_tab_t **)chanid);
+
+ /* We should have multiple callers for a particular channel,
+ * an interrupt doesn't affect this pointer nor the descriptor,
+ * so no locking should be needed.
+ */
+ dp = ctp->put_ptr;
+
+ /* If the descriptor is valid, we are way ahead of the DMA
+ * engine, so just return an error condition.
+ */
+ if (dp->dscr_cmd0 & DSCR_CMD0_V) {
+ return 0;
+ }
+
+ /* Load up buffer address and byte count.
+ */
+ dp->dscr_source0 = virt_to_phys(buf);
+ dp->dscr_cmd1 = nbytes;
+ dp->dscr_cmd0 |= DSCR_CMD0_V; /* Let it rip */
+ ctp->chan_ptr->ddma_dbell = 0xffffffff; /* Make it go */
+
+ /* Get next descriptor pointer.
+ */
+ ctp->put_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
+
+ /* return something not zero.
+ */
+ return nbytes;
+}
+
+/* Put a destination buffer into the DMA ring.
+ * This updates the destination pointer and byte count. Normally used
+ * to place an empty buffer into the ring for fifo to memory transfers.
+ */
+u32
+au1xxx_dbdma_put_dest(u32 chanid, void *buf, int nbytes)
+{
+ chan_tab_t *ctp;
+ au1x_ddma_desc_t *dp;
+
+ /* I guess we could check this to be within the
+ * range of the table......
+ */
+ ctp = *((chan_tab_t **)chanid);
+
+ /* We should have multiple callers for a particular channel,
+ * an interrupt doesn't affect this pointer nor the descriptor,
+ * so no locking should be needed.
+ */
+ dp = ctp->put_ptr;
+
+ /* If the descriptor is valid, we are way ahead of the DMA
+ * engine, so just return an error condition.
+ */
+ if (dp->dscr_cmd0 & DSCR_CMD0_V)
+ return 0;
+
+ /* Load up buffer address and byte count.
+ */
+ dp->dscr_dest0 = virt_to_phys(buf);
+ dp->dscr_cmd1 = nbytes;
+ dp->dscr_cmd0 |= DSCR_CMD0_V; /* Let it rip */
+
+ /* Get next descriptor pointer.
+ */
+ ctp->put_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
+
+ /* return something not zero.
+ */
+ return nbytes;
+}
+
+/* Get a destination buffer into the DMA ring.
+ * Normally used to get a full buffer from the ring during fifo
+ * to memory transfers. This does not set the valid bit, you will
+ * have to put another destination buffer to keep the DMA going.
+ */
+u32
+au1xxx_dbdma_get_dest(u32 chanid, void **buf, int *nbytes)
+{
+ chan_tab_t *ctp;
+ au1x_ddma_desc_t *dp;
+ u32 rv;
+
+ /* I guess we could check this to be within the
+ * range of the table......
+ */
+ ctp = *((chan_tab_t **)chanid);
+
+ /* We should have multiple callers for a particular channel,
+ * an interrupt doesn't affect this pointer nor the descriptor,
+ * so no locking should be needed.
+ */
+ dp = ctp->get_ptr;
+
+ /* If the descriptor is valid, we are way ahead of the DMA
+ * engine, so just return an error condition.
+ */
+ if (dp->dscr_cmd0 & DSCR_CMD0_V)
+ return 0;
+
+ /* Return buffer address and byte count.
+ */
+ *buf = (void *)(phys_to_virt(dp->dscr_dest0));
+ *nbytes = dp->dscr_cmd1;
+ rv = dp->dscr_stat;
+
+ /* Get next descriptor pointer.
+ */
+ ctp->get_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
+
+ /* return something not zero.
+ */
+ return rv;
+}
+
+void
+au1xxx_dbdma_stop(u32 chanid)
+{
+ chan_tab_t *ctp;
+ volatile au1x_dma_chan_t *cp;
+ int halt_timeout = 0;
+
+ ctp = *((chan_tab_t **)chanid);
+
+ cp = ctp->chan_ptr;
+ cp->ddma_cfg &= ~DDMA_CFG_EN; /* Disable channel */
+ au_sync();
+ while (!(cp->ddma_stat & DDMA_STAT_H)) {
+ udelay(1);
+ halt_timeout++;
+ if (halt_timeout > 100) {
+ printk("warning: DMA channel won't halt\n");
+ break;
+ }
+ }
+ /* clear current desc valid and doorbell */
+ cp->ddma_stat |= (DDMA_STAT_DB | DDMA_STAT_V);
+ au_sync();
+}
+
+/* Start using the current descriptor pointer. If the dbdma encounters
+ * a not valid descriptor, it will stop. In this case, we can just
+ * continue by adding a buffer to the list and starting again.
+ */
+void
+au1xxx_dbdma_start(u32 chanid)
+{
+ chan_tab_t *ctp;
+ volatile au1x_dma_chan_t *cp;
+
+ ctp = *((chan_tab_t **)chanid);
+
+ cp = ctp->chan_ptr;
+ cp->ddma_desptr = virt_to_phys(ctp->cur_ptr);
+ cp->ddma_cfg |= DDMA_CFG_EN; /* Enable channel */
+ au_sync();
+ cp->ddma_dbell = 0xffffffff; /* Make it go */
+ au_sync();
+}
+
+void
+au1xxx_dbdma_reset(u32 chanid)
+{
+ chan_tab_t *ctp;
+ au1x_ddma_desc_t *dp;
+
+ au1xxx_dbdma_stop(chanid);
+
+ ctp = *((chan_tab_t **)chanid);
+ ctp->get_ptr = ctp->put_ptr = ctp->cur_ptr = ctp->chan_desc_base;
+
+ /* Run through the descriptors and reset the valid indicator.
+ */
+ dp = ctp->chan_desc_base;
+
+ do {
+ dp->dscr_cmd0 &= ~DSCR_CMD0_V;
+ dp = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
+ } while (dp != ctp->chan_desc_base);
+}
+
+u32
+au1xxx_get_dma_residue(u32 chanid)
+{
+ chan_tab_t *ctp;
+ volatile au1x_dma_chan_t *cp;
+ u32 rv;
+
+ ctp = *((chan_tab_t **)chanid);
+ cp = ctp->chan_ptr;
+
+ /* This is only valid if the channel is stopped.
+ */
+ rv = cp->ddma_bytecnt;
+ au_sync();
+
+ return rv;
+}
+
+void
+au1xxx_dbdma_chan_free(u32 chanid)
+{
+ chan_tab_t *ctp;
+ dbdev_tab_t *stp, *dtp;
+
+ ctp = *((chan_tab_t **)chanid);
+ stp = ctp->chan_src;
+ dtp = ctp->chan_dest;
+
+ au1xxx_dbdma_stop(chanid);
+
+ if (ctp->chan_desc_base != NULL)
+ kfree(ctp->chan_desc_base);
+
+ stp->dev_flags &= ~DEV_FLAGS_INUSE;
+ dtp->dev_flags &= ~DEV_FLAGS_INUSE;
+ chan_tab_ptr[ctp->chan_index] = NULL;
+
+ kfree(ctp);
+}
+
+static irqreturn_t
+dbdma_interrupt(int irq, void *dev_id, struct pt_regs *regs)
+{
+ u32 intstat;
+ u32 chan_index;
+ chan_tab_t *ctp;
+ au1x_ddma_desc_t *dp;
+ volatile au1x_dma_chan_t *cp;
+
+ intstat = dbdma_gptr->ddma_intstat;
+ au_sync();
+ chan_index = au_ffs(intstat) - 1;
+
+ ctp = chan_tab_ptr[chan_index];
+ cp = ctp->chan_ptr;
+ dp = ctp->cur_ptr;
+
+ /* Reset interrupt.
+ */
+ cp->ddma_irq = 0;
+ au_sync();
+
+ if (ctp->chan_callback)
+ (ctp->chan_callback)(irq, ctp->chan_callparam, regs);
+
+ ctp->cur_ptr = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
+
+ return IRQ_HANDLED;
+}
+
+static void
+au1xxx_dbdma_init(void)
+{
+ dbdma_gptr->ddma_config = 0;
+ dbdma_gptr->ddma_throttle = 0;
+ dbdma_gptr->ddma_inten = 0xffff;
+ au_sync();
+
+ if (request_irq(AU1550_DDMA_INT, dbdma_interrupt, SA_INTERRUPT,
+ "Au1xxx dbdma", (void *)dbdma_gptr))
+ printk("Can't get 1550 dbdma irq");
+}
+
+void
+au1xxx_dbdma_dump(u32 chanid)
+{
+ chan_tab_t *ctp;
+ au1x_ddma_desc_t *dp;
+ dbdev_tab_t *stp, *dtp;
+ volatile au1x_dma_chan_t *cp;
+
+ ctp = *((chan_tab_t **)chanid);
+ stp = ctp->chan_src;
+ dtp = ctp->chan_dest;
+ cp = ctp->chan_ptr;
+
+ printk("Chan %x, stp %x (dev %d) dtp %x (dev %d) \n",
+ (u32)ctp, (u32)stp, stp - dbdev_tab, (u32)dtp, dtp - dbdev_tab);
+ printk("desc base %x, get %x, put %x, cur %x\n",
+ (u32)(ctp->chan_desc_base), (u32)(ctp->get_ptr),
+ (u32)(ctp->put_ptr), (u32)(ctp->cur_ptr));
+
+ printk("dbdma chan %x\n", (u32)cp);
+ printk("cfg %08x, desptr %08x, statptr %08x\n",
+ cp->ddma_cfg, cp->ddma_desptr, cp->ddma_statptr);
+ printk("dbell %08x, irq %08x, stat %08x, bytecnt %08x\n",
+ cp->ddma_dbell, cp->ddma_irq, cp->ddma_stat, cp->ddma_bytecnt);
+
+
+ /* Run through the descriptors
+ */
+ dp = ctp->chan_desc_base;
+
+ do {
+ printk("dp %08x, cmd0 %08x, cmd1 %08x\n",
+ (u32)dp, dp->dscr_cmd0, dp->dscr_cmd1);
+ printk("src0 %08x, src1 %08x, dest0 %08x\n",
+ dp->dscr_source0, dp->dscr_source1, dp->dscr_dest0);
+ printk("dest1 %08x, stat %08x, nxtptr %08x\n",
+ dp->dscr_dest1, dp->dscr_stat, dp->dscr_nxtptr);
+ dp = phys_to_virt(DSCR_GET_NXTPTR(dp->dscr_nxtptr));
+ } while (dp != ctp->chan_desc_base);
+}
+
+#endif /* defined(CONFIG_SOC_AU1550) || defined(CONFIG_SOC_AU1200) */
+
diff --git a/arch/mips/au1000/common/dbg_io.c b/arch/mips/au1000/common/dbg_io.c
new file mode 100644
index 00000000000..7bc768e558d
--- /dev/null
+++ b/arch/mips/au1000/common/dbg_io.c
@@ -0,0 +1,122 @@
+
+#include <linux/config.h>
+#include <asm/io.h>
+#include <asm/mach-au1x00/au1000.h>
+
+#ifdef CONFIG_KGDB
+
+/*
+ * FIXME the user should be able to select the
+ * uart to be used for debugging.
+ */
+#define DEBUG_BASE UART_DEBUG_BASE
+/**/
+
+/* we need uint32 uint8 */
+/* #include "types.h" */
+typedef unsigned char uint8;
+typedef unsigned int uint32;
+
+#define UART16550_BAUD_2400 2400
+#define UART16550_BAUD_4800 4800
+#define UART16550_BAUD_9600 9600
+#define UART16550_BAUD_19200 19200
+#define UART16550_BAUD_38400 38400
+#define UART16550_BAUD_57600 57600
+#define UART16550_BAUD_115200 115200
+
+#define UART16550_PARITY_NONE 0
+#define UART16550_PARITY_ODD 0x08
+#define UART16550_PARITY_EVEN 0x18
+#define UART16550_PARITY_MARK 0x28
+#define UART16550_PARITY_SPACE 0x38
+
+#define UART16550_DATA_5BIT 0x0
+#define UART16550_DATA_6BIT 0x1
+#define UART16550_DATA_7BIT 0x2
+#define UART16550_DATA_8BIT 0x3
+
+#define UART16550_STOP_1BIT 0x0
+#define UART16550_STOP_2BIT 0x4
+
+
+#define UART_RX 0 /* Receive buffer */
+#define UART_TX 4 /* Transmit buffer */
+#define UART_IER 8 /* Interrupt Enable Register */
+#define UART_IIR 0xC /* Interrupt ID Register */
+#define UART_FCR 0x10 /* FIFO Control Register */
+#define UART_LCR 0x14 /* Line Control Register */
+#define UART_MCR 0x18 /* Modem Control Register */
+#define UART_LSR 0x1C /* Line Status Register */
+#define UART_MSR 0x20 /* Modem Status Register */
+#define UART_CLK 0x28 /* Baud Rat4e Clock Divider */
+#define UART_MOD_CNTRL 0x100 /* Module Control */
+
+/* memory-mapped read/write of the port */
+#define UART16550_READ(y) (au_readl(DEBUG_BASE + y) & 0xff)
+#define UART16550_WRITE(y,z) (au_writel(z&0xff, DEBUG_BASE + y))
+
+extern unsigned long get_au1x00_uart_baud_base(void);
+extern unsigned long cal_r4koff(void);
+
+void debugInit(uint32 baud, uint8 data, uint8 parity, uint8 stop)
+{
+
+ if (UART16550_READ(UART_MOD_CNTRL) != 0x3) {
+ UART16550_WRITE(UART_MOD_CNTRL, 3);
+ }
+ cal_r4koff();
+
+ /* disable interrupts */
+ UART16550_WRITE(UART_IER, 0);
+
+ /* set up baud rate */
+ {
+ uint32 divisor;
+
+ /* set divisor */
+ divisor = get_au1x00_uart_baud_base() / baud;
+ UART16550_WRITE(UART_CLK, divisor & 0xffff);
+ }
+
+ /* set data format */
+ UART16550_WRITE(UART_LCR, (data | parity | stop));
+}
+
+static int remoteDebugInitialized = 0;
+
+uint8 getDebugChar(void)
+{
+ if (!remoteDebugInitialized) {
+ remoteDebugInitialized = 1;
+ debugInit(UART16550_BAUD_115200,
+ UART16550_DATA_8BIT,
+ UART16550_PARITY_NONE,
+ UART16550_STOP_1BIT);
+ }
+
+ while((UART16550_READ(UART_LSR) & 0x1) == 0);
+ return UART16550_READ(UART_RX);
+}
+
+
+int putDebugChar(uint8 byte)
+{
+// int i;
+
+ if (!remoteDebugInitialized) {
+ remoteDebugInitialized = 1;
+ debugInit(UART16550_BAUD_115200,
+ UART16550_DATA_8BIT,
+ UART16550_PARITY_NONE,
+ UART16550_STOP_1BIT);
+ }
+
+ while ((UART16550_READ(UART_LSR)&0x40) == 0);
+ UART16550_WRITE(UART_TX, byte);
+ //for (i=0;i<0xfff;i++);
+
+ return 1;
+}
+
+#endif
diff --git a/arch/mips/au1000/common/dma.c b/arch/mips/au1000/common/dma.c
new file mode 100644
index 00000000000..372c33f1353
--- /dev/null
+++ b/arch/mips/au1000/common/dma.c
@@ -0,0 +1,243 @@
+/*
+ *
+ * BRIEF MODULE DESCRIPTION
+ * A DMA channel allocator for Au1000. API is modeled loosely off of
+ * linux/kernel/dma.c.
+ *
+ * Copyright 2000 MontaVista Software Inc.
+ * Author: MontaVista Software, Inc.
+ * stevel@mvista.com or source@mvista.com
+ * Copyright (C) 2005 Ralf Baechle (ralf@linux-mips.org)
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ *
+ */
+#include <linux/config.h>
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/sched.h>
+#include <linux/spinlock.h>
+#include <linux/string.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+#include <linux/module.h>
+#include <asm/system.h>
+#include <asm/mach-au1x00/au1000.h>
+#include <asm/mach-au1x00/au1000_dma.h>
+
+#if defined(CONFIG_SOC_AU1000) || defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1100)
+/*
+ * A note on resource allocation:
+ *
+ * All drivers needing DMA channels, should allocate and release them
+ * through the public routines `request_dma()' and `free_dma()'.
+ *
+ * In order to avoid problems, all processes should allocate resources in
+ * the same sequence and release them in the reverse order.
+ *
+ * So, when allocating DMAs and IRQs, first allocate the DMA, then the IRQ.
+ * When releasing them, first release the IRQ, then release the DMA. The
+ * main reason for this order is that, if you are requesting the DMA buffer
+ * done interrupt, you won't know the irq number until the DMA channel is
+ * returned from request_dma.
+ */
+
+
+DEFINE_SPINLOCK(au1000_dma_spin_lock);
+
+struct dma_chan au1000_dma_table[NUM_AU1000_DMA_CHANNELS] = {
+ {.dev_id = -1,},
+ {.dev_id = -1,},
+ {.dev_id = -1,},
+ {.dev_id = -1,},
+ {.dev_id = -1,},
+ {.dev_id = -1,},
+ {.dev_id = -1,},
+ {.dev_id = -1,}
+};
+EXPORT_SYMBOL(au1000_dma_table);
+
+// Device FIFO addresses and default DMA modes
+static const struct dma_dev {
+ unsigned int fifo_addr;
+ unsigned int dma_mode;
+} dma_dev_table[DMA_NUM_DEV] = {
+ {UART0_ADDR + UART_TX, 0},
+ {UART0_ADDR + UART_RX, 0},
+ {0, 0},
+ {0, 0},
+ {AC97C_DATA, DMA_DW16 }, // coherent
+ {AC97C_DATA, DMA_DR | DMA_DW16 }, // coherent
+ {UART3_ADDR + UART_TX, DMA_DW8 | DMA_NC},
+ {UART3_ADDR + UART_RX, DMA_DR | DMA_DW8 | DMA_NC},
+ {USBD_EP0RD, DMA_DR | DMA_DW8 | DMA_NC},
+ {USBD_EP0WR, DMA_DW8 | DMA_NC},
+ {USBD_EP2WR, DMA_DW8 | DMA_NC},
+ {USBD_EP3WR, DMA_DW8 | DMA_NC},
+ {USBD_EP4RD, DMA_DR | DMA_DW8 | DMA_NC},
+ {USBD_EP5RD, DMA_DR | DMA_DW8 | DMA_NC},
+ {I2S_DATA, DMA_DW32 | DMA_NC},
+ {I2S_DATA, DMA_DR | DMA_DW32 | DMA_NC}
+};
+
+int au1000_dma_read_proc(char *buf, char **start, off_t fpos,
+ int length, int *eof, void *data)
+{
+ int i, len = 0;
+ struct dma_chan *chan;
+
+ for (i = 0; i < NUM_AU1000_DMA_CHANNELS; i++) {
+ if ((chan = get_dma_chan(i)) != NULL) {
+ len += sprintf(buf + len, "%2d: %s\n",
+ i, chan->dev_str);
+ }
+ }
+
+ if (fpos >= len) {
+ *start = buf;
+ *eof = 1;
+ return 0;
+ }
+ *start = buf + fpos;
+ if ((len -= fpos) > length)
+ return length;
+ *eof = 1;
+ return len;
+}
+
+// Device FIFO addresses and default DMA modes - 2nd bank
+static const struct dma_dev dma_dev_table_bank2[DMA_NUM_DEV_BANK2] = {
+ {SD0_XMIT_FIFO, DMA_DS | DMA_DW8}, // coherent
+ {SD0_RECV_FIFO, DMA_DS | DMA_DR | DMA_DW8}, // coherent
+ {SD1_XMIT_FIFO, DMA_DS | DMA_DW8}, // coherent
+ {SD1_RECV_FIFO, DMA_DS | DMA_DR | DMA_DW8} // coherent
+};
+
+void dump_au1000_dma_channel(unsigned int dmanr)
+{
+ struct dma_chan *chan;
+
+ if (dmanr >= NUM_AU1000_DMA_CHANNELS)
+ return;
+ chan = &au1000_dma_table[dmanr];
+
+ printk(KERN_INFO "Au1000 DMA%d Register Dump:\n", dmanr);
+ printk(KERN_INFO " mode = 0x%08x\n",
+ au_readl(chan->io + DMA_MODE_SET));
+ printk(KERN_INFO " addr = 0x%08x\n",
+ au_readl(chan->io + DMA_PERIPHERAL_ADDR));
+ printk(KERN_INFO " start0 = 0x%08x\n",
+ au_readl(chan->io + DMA_BUFFER0_START));
+ printk(KERN_INFO " start1 = 0x%08x\n",
+ au_readl(chan->io + DMA_BUFFER1_START));
+ printk(KERN_INFO " count0 = 0x%08x\n",
+ au_readl(chan->io + DMA_BUFFER0_COUNT));
+ printk(KERN_INFO " count1 = 0x%08x\n",
+ au_readl(chan->io + DMA_BUFFER1_COUNT));
+}
+
+
+/*
+ * Finds a free channel, and binds the requested device to it.
+ * Returns the allocated channel number, or negative on error.
+ * Requests the DMA done IRQ if irqhandler != NULL.
+ */
+int request_au1000_dma(int dev_id, const char *dev_str,
+ irqreturn_t (*irqhandler)(int, void *, struct pt_regs *),
+ unsigned long irqflags,
+ void *irq_dev_id)
+{
+ struct dma_chan *chan;
+ const struct dma_dev *dev;
+ int i, ret;
+
+#if defined(CONFIG_SOC_AU1100)
+ if (dev_id < 0 || dev_id >= (DMA_NUM_DEV + DMA_NUM_DEV_BANK2))
+ return -EINVAL;
+#else
+ if (dev_id < 0 || dev_id >= DMA_NUM_DEV)
+ return -EINVAL;
+#endif
+
+ for (i = 0; i < NUM_AU1000_DMA_CHANNELS; i++) {
+ if (au1000_dma_table[i].dev_id < 0)
+ break;
+ }
+ if (i == NUM_AU1000_DMA_CHANNELS)
+ return -ENODEV;
+
+ chan = &au1000_dma_table[i];
+
+ if (dev_id >= DMA_NUM_DEV) {
+ dev_id -= DMA_NUM_DEV;
+ dev = &dma_dev_table_bank2[dev_id];
+ } else {
+ dev = &dma_dev_table[dev_id];
+ }
+
+ if (irqhandler) {
+ chan->irq = AU1000_DMA_INT_BASE + i;
+ chan->irq_dev = irq_dev_id;
+ if ((ret = request_irq(chan->irq, irqhandler, irqflags,
+ dev_str, chan->irq_dev))) {
+ chan->irq = 0;
+ chan->irq_dev = NULL;
+ return ret;
+ }
+ } else {
+ chan->irq = 0;
+ chan->irq_dev = NULL;
+ }
+
+ // fill it in
+ chan->io = DMA_CHANNEL_BASE + i * DMA_CHANNEL_LEN;
+ chan->dev_id = dev_id;
+ chan->dev_str = dev_str;
+ chan->fifo_addr = dev->fifo_addr;
+ chan->mode = dev->dma_mode;
+
+ /* initialize the channel before returning */
+ init_dma(i);
+
+ return i;
+}
+EXPORT_SYMBOL(request_au1000_dma);
+
+void free_au1000_dma(unsigned int dmanr)
+{
+ struct dma_chan *chan = get_dma_chan(dmanr);
+ if (!chan) {
+ printk("Trying to free DMA%d\n", dmanr);
+ return;
+ }
+
+ disable_dma(dmanr);
+ if (chan->irq)
+ free_irq(chan->irq, chan->irq_dev);
+
+ chan->irq = 0;
+ chan->irq_dev = NULL;
+ chan->dev_id = -1;
+}
+EXPORT_SYMBOL(free_au1000_dma);
+
+#endif // AU1000 AU1500 AU1100
diff --git a/arch/mips/au1000/common/int-handler.S b/arch/mips/au1000/common/int-handler.S
new file mode 100644
index 00000000000..1c4ca883321
--- /dev/null
+++ b/arch/mips/au1000/common/int-handler.S
@@ -0,0 +1,68 @@
+/*
+ * Copyright 2001 MontaVista Software Inc.
+ * Author: ppopov@mvista.com
+ *
+ * Interrupt dispatcher for Au1000 boards.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+#include <asm/asm.h>
+#include <asm/mipsregs.h>
+#include <asm/addrspace.h>
+#include <asm/regdef.h>
+#include <asm/stackframe.h>
+
+ .text
+ .set macro
+ .set noat
+ .align 5
+
+NESTED(au1000_IRQ, PT_SIZE, sp)
+ SAVE_ALL
+ CLI # Important: mark KERNEL mode !
+
+ mfc0 t0,CP0_CAUSE # get pending interrupts
+ mfc0 t1,CP0_STATUS # get enabled interrupts
+ and t0,t1 # isolate allowed ones
+
+ andi t0,0xff00 # isolate pending bits
+ beqz t0, 3f # spurious interrupt
+
+ andi a0, t0, CAUSEF_IP7
+ beq a0, zero, 1f
+ move a0, sp
+ jal mips_timer_interrupt
+ j ret_from_irq
+
+1:
+ andi a0, t0, CAUSEF_IP2 # Interrupt Controller 0, Request 0
+ beq a0, zero, 2f
+ move a0,sp
+ jal intc0_req0_irqdispatch
+ j ret_from_irq
+2:
+ andi a0, t0, CAUSEF_IP3 # Interrupt Controller 0, Request 1
+ beq a0, zero, 3f
+ move a0,sp
+ jal intc0_req1_irqdispatch
+ j ret_from_irq
+3:
+ andi a0, t0, CAUSEF_IP4 # Interrupt Controller 1, Request 0
+ beq a0, zero, 4f
+ move a0,sp
+ jal intc1_req0_irqdispatch
+ j ret_from_irq
+4:
+ andi a0, t0, CAUSEF_IP5 # Interrupt Controller 1, Request 1
+ beq a0, zero, 5f
+ move a0, sp
+ jal intc1_req1_irqdispatch
+ j ret_from_irq
+
+5:
+ move a0, sp
+ j spurious_interrupt
+END(au1000_IRQ)
diff --git a/arch/mips/au1000/common/irq.c b/arch/mips/au1000/common/irq.c
new file mode 100644
index 00000000000..d1eb5a4a9a1
--- /dev/null
+++ b/arch/mips/au1000/common/irq.c
@@ -0,0 +1,654 @@
+/*
+ * BRIEF MODULE DESCRIPTION
+ * Au1000 interrupt routines.
+ *
+ * Copyright 2001 MontaVista Software Inc.
+ * Author: MontaVista Software, Inc.
+ * ppopov@mvista.com or source@mvista.com
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#include <linux/config.h>
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/irq.h>
+#include <linux/kernel_stat.h>
+#include <linux/module.h>
+#include <linux/signal.h>
+#include <linux/sched.h>
+#include <linux/types.h>
+#include <linux/interrupt.h>
+#include <linux/ioport.h>
+#include <linux/timex.h>
+#include <linux/slab.h>
+#include <linux/random.h>
+#include <linux/delay.h>
+#include <linux/bitops.h>
+
+#include <asm/bootinfo.h>
+#include <asm/io.h>
+#include <asm/mipsregs.h>
+#include <asm/system.h>
+#include <asm/mach-au1x00/au1000.h>
+#ifdef CONFIG_MIPS_PB1000
+#include <asm/mach-pb1x00/pb1000.h>
+#endif
+
+#undef DEBUG_IRQ
+#ifdef DEBUG_IRQ
+/* note: prints function name for you */
+#define DPRINTK(fmt, args...) printk("%s: " fmt, __FUNCTION__ , ## args)
+#else
+#define DPRINTK(fmt, args...)
+#endif
+
+#define EXT_INTC0_REQ0 2 /* IP 2 */
+#define EXT_INTC0_REQ1 3 /* IP 3 */
+#define EXT_INTC1_REQ0 4 /* IP 4 */
+#define EXT_INTC1_REQ1 5 /* IP 5 */
+#define MIPS_TIMER_IP 7 /* IP 7 */
+
+extern asmlinkage void au1000_IRQ(void);
+extern void set_debug_traps(void);
+extern irq_cpustat_t irq_stat [NR_CPUS];
+
+static void setup_local_irq(unsigned int irq, int type, int int_req);
+static unsigned int startup_irq(unsigned int irq);
+static void end_irq(unsigned int irq_nr);
+static inline void mask_and_ack_level_irq(unsigned int irq_nr);
+static inline void mask_and_ack_rise_edge_irq(unsigned int irq_nr);
+static inline void mask_and_ack_fall_edge_irq(unsigned int irq_nr);
+static inline void mask_and_ack_either_edge_irq(unsigned int irq_nr);
+inline void local_enable_irq(unsigned int irq_nr);
+inline void local_disable_irq(unsigned int irq_nr);
+
+void (*board_init_irq)(void);
+
+#ifdef CONFIG_PM
+extern void counter0_irq(int irq, void *dev_id, struct pt_regs *regs);
+#endif
+
+static DEFINE_SPINLOCK(irq_lock);
+
+
+static unsigned int startup_irq(unsigned int irq_nr)
+{
+ local_enable_irq(irq_nr);
+ return 0;
+}
+
+
+static void shutdown_irq(unsigned int irq_nr)
+{
+ local_disable_irq(irq_nr);
+ return;
+}
+
+
+inline void local_enable_irq(unsigned int irq_nr)
+{
+ if (irq_nr > AU1000_LAST_INTC0_INT) {
+ au_writel(1<<(irq_nr-32), IC1_MASKSET);
+ au_writel(1<<(irq_nr-32), IC1_WAKESET);
+ }
+ else {
+ au_writel(1<<irq_nr, IC0_MASKSET);
+ au_writel(1<<irq_nr, IC0_WAKESET);
+ }
+ au_sync();
+}
+
+
+inline void local_disable_irq(unsigned int irq_nr)
+{
+ if (irq_nr > AU1000_LAST_INTC0_INT) {
+ au_writel(1<<(irq_nr-32), IC1_MASKCLR);
+ au_writel(1<<(irq_nr-32), IC1_WAKECLR);
+ }
+ else {
+ au_writel(1<<irq_nr, IC0_MASKCLR);
+ au_writel(1<<irq_nr, IC0_WAKECLR);
+ }
+ au_sync();
+}
+
+
+static inline void mask_and_ack_rise_edge_irq(unsigned int irq_nr)
+{
+ if (irq_nr > AU1000_LAST_INTC0_INT) {
+ au_writel(1<<(irq_nr-32), IC1_RISINGCLR);
+ au_writel(1<<(irq_nr-32), IC1_MASKCLR);
+ }
+ else {
+ au_writel(1<<irq_nr, IC0_RISINGCLR);
+ au_writel(1<<irq_nr, IC0_MASKCLR);
+ }
+ au_sync();
+}
+
+
+static inline void mask_and_ack_fall_edge_irq(unsigned int irq_nr)
+{
+ if (irq_nr > AU1000_LAST_INTC0_INT) {
+ au_writel(1<<(irq_nr-32), IC1_FALLINGCLR);
+ au_writel(1<<(irq_nr-32), IC1_MASKCLR);
+ }
+ else {
+ au_writel(1<<irq_nr, IC0_FALLINGCLR);
+ au_writel(1<<irq_nr, IC0_MASKCLR);
+ }
+ au_sync();
+}
+
+
+static inline void mask_and_ack_either_edge_irq(unsigned int irq_nr)
+{
+ /* This may assume that we don't get interrupts from
+ * both edges at once, or if we do, that we don't care.
+ */
+ if (irq_nr > AU1000_LAST_INTC0_INT) {
+ au_writel(1<<(irq_nr-32), IC1_FALLINGCLR);
+ au_writel(1<<(irq_nr-32), IC1_RISINGCLR);
+ au_writel(1<<(irq_nr-32), IC1_MASKCLR);
+ }
+ else {
+ au_writel(1<<irq_nr, IC0_FALLINGCLR);
+ au_writel(1<<irq_nr, IC0_RISINGCLR);
+ au_writel(1<<irq_nr, IC0_MASKCLR);
+ }
+ au_sync();
+}
+
+
+static inline void mask_and_ack_level_irq(unsigned int irq_nr)
+{
+
+ local_disable_irq(irq_nr);
+ au_sync();
+#if defined(CONFIG_MIPS_PB1000)
+ if (irq_nr == AU1000_GPIO_15) {
+ au_writel(0x8000, PB1000_MDR); /* ack int */
+ au_sync();
+ }
+#endif
+ return;
+}
+
+
+static void end_irq(unsigned int irq_nr)
+{
+ if (!(irq_desc[irq_nr].status & (IRQ_DISABLED|IRQ_INPROGRESS))) {
+ local_enable_irq(irq_nr);
+ }
+#if defined(CONFIG_MIPS_PB1000)
+ if (irq_nr == AU1000_GPIO_15) {
+ au_writel(0x4000, PB1000_MDR); /* enable int */
+ au_sync();
+ }
+#endif
+}
+
+unsigned long save_local_and_disable(int controller)
+{
+ int i;
+ unsigned long flags, mask;
+
+ spin_lock_irqsave(&irq_lock, flags);
+ if (controller) {
+ mask = au_readl(IC1_MASKSET);
+ for (i=32; i<64; i++) {
+ local_disable_irq(i);
+ }
+ }
+ else {
+ mask = au_readl(IC0_MASKSET);
+ for (i=0; i<32; i++) {
+ local_disable_irq(i);
+ }
+ }
+ spin_unlock_irqrestore(&irq_lock, flags);
+
+ return mask;
+}
+
+void restore_local_and_enable(int controller, unsigned long mask)
+{
+ int i;
+ unsigned long flags, new_mask;
+
+ spin_lock_irqsave(&irq_lock, flags);
+ for (i=0; i<32; i++) {
+ if (mask & (1<<i)) {
+ if (controller)
+ local_enable_irq(i+32);
+ else
+ local_enable_irq(i);
+ }
+ }
+ if (controller)
+ new_mask = au_readl(IC1_MASKSET);
+ else
+ new_mask = au_readl(IC0_MASKSET);
+
+ spin_unlock_irqrestore(&irq_lock, flags);
+}
+
+
+static struct hw_interrupt_type rise_edge_irq_type = {
+ "Au1000 Rise Edge",
+ startup_irq,
+ shutdown_irq,
+ local_enable_irq,
+ local_disable_irq,
+ mask_and_ack_rise_edge_irq,
+ end_irq,
+ NULL
+};
+
+static struct hw_interrupt_type fall_edge_irq_type = {
+ "Au1000 Fall Edge",
+ startup_irq,
+ shutdown_irq,
+ local_enable_irq,
+ local_disable_irq,
+ mask_and_ack_fall_edge_irq,
+ end_irq,
+ NULL
+};
+
+static struct hw_interrupt_type either_edge_irq_type = {
+ "Au1000 Rise or Fall Edge",
+ startup_irq,
+ shutdown_irq,
+ local_enable_irq,
+ local_disable_irq,
+ mask_and_ack_either_edge_irq,
+ end_irq,
+ NULL
+};
+
+static struct hw_interrupt_type level_irq_type = {
+ "Au1000 Level",
+ startup_irq,
+ shutdown_irq,
+ local_enable_irq,
+ local_disable_irq,
+ mask_and_ack_level_irq,
+ end_irq,
+ NULL
+};
+
+#ifdef CONFIG_PM
+void startup_match20_interrupt(void)
+{
+ local_enable_irq(AU1000_TOY_MATCH2_INT);
+}
+#endif
+
+static void setup_local_irq(unsigned int irq_nr, int type, int int_req)
+{
+ if (irq_nr > AU1000_MAX_INTR) return;
+ /* Config2[n], Config1[n], Config0[n] */
+ if (irq_nr > AU1000_LAST_INTC0_INT) {
+ switch (type) {
+ case INTC_INT_RISE_EDGE: /* 0:0:1 */
+ au_writel(1<<(irq_nr-32), IC1_CFG2CLR);
+ au_writel(1<<(irq_nr-32), IC1_CFG1CLR);
+ au_writel(1<<(irq_nr-32), IC1_CFG0SET);
+ irq_desc[irq_nr].handler = &rise_edge_irq_type;
+ break;
+ case INTC_INT_FALL_EDGE: /* 0:1:0 */
+ au_writel(1<<(irq_nr-32), IC1_CFG2CLR);
+ au_writel(1<<(irq_nr-32), IC1_CFG1SET);
+ au_writel(1<<(irq_nr-32), IC1_CFG0CLR);
+ irq_desc[irq_nr].handler = &fall_edge_irq_type;
+ break;
+ case INTC_INT_RISE_AND_FALL_EDGE: /* 0:1:1 */
+ au_writel(1<<(irq_nr-32), IC1_CFG2CLR);
+ au_writel(1<<(irq_nr-32), IC1_CFG1SET);
+ au_writel(1<<(irq_nr-32), IC1_CFG0SET);
+ irq_desc[irq_nr].handler = &either_edge_irq_type;
+ break;
+ case INTC_INT_HIGH_LEVEL: /* 1:0:1 */
+ au_writel(1<<(irq_nr-32), IC1_CFG2SET);
+ au_writel(1<<(irq_nr-32), IC1_CFG1CLR);
+ au_writel(1<<(irq_nr-32), IC1_CFG0SET);
+ irq_desc[irq_nr].handler = &level_irq_type;
+ break;
+ case INTC_INT_LOW_LEVEL: /* 1:1:0 */
+ au_writel(1<<(irq_nr-32), IC1_CFG2SET);
+ au_writel(1<<(irq_nr-32), IC1_CFG1SET);
+ au_writel(1<<(irq_nr-32), IC1_CFG0CLR);
+ irq_desc[irq_nr].handler = &level_irq_type;
+ break;
+ case INTC_INT_DISABLED: /* 0:0:0 */
+ au_writel(1<<(irq_nr-32), IC1_CFG0CLR);
+ au_writel(1<<(irq_nr-32), IC1_CFG1CLR);
+ au_writel(1<<(irq_nr-32), IC1_CFG2CLR);
+ break;
+ default: /* disable the interrupt */
+ printk("unexpected int type %d (irq %d)\n", type, irq_nr);
+ au_writel(1<<(irq_nr-32), IC1_CFG0CLR);
+ au_writel(1<<(irq_nr-32), IC1_CFG1CLR);
+ au_writel(1<<(irq_nr-32), IC1_CFG2CLR);
+ return;
+ }
+ if (int_req) /* assign to interrupt request 1 */
+ au_writel(1<<(irq_nr-32), IC1_ASSIGNCLR);
+ else /* assign to interrupt request 0 */
+ au_writel(1<<(irq_nr-32), IC1_ASSIGNSET);
+ au_writel(1<<(irq_nr-32), IC1_SRCSET);
+ au_writel(1<<(irq_nr-32), IC1_MASKCLR);
+ au_writel(1<<(irq_nr-32), IC1_WAKECLR);
+ }
+ else {
+ switch (type) {
+ case INTC_INT_RISE_EDGE: /* 0:0:1 */
+ au_writel(1<<irq_nr, IC0_CFG2CLR);
+ au_writel(1<<irq_nr, IC0_CFG1CLR);
+ au_writel(1<<irq_nr, IC0_CFG0SET);
+ irq_desc[irq_nr].handler = &rise_edge_irq_type;
+ break;
+ case INTC_INT_FALL_EDGE: /* 0:1:0 */
+ au_writel(1<<irq_nr, IC0_CFG2CLR);
+ au_writel(1<<irq_nr, IC0_CFG1SET);
+ au_writel(1<<irq_nr, IC0_CFG0CLR);
+ irq_desc[irq_nr].handler = &fall_edge_irq_type;
+ break;
+ case INTC_INT_RISE_AND_FALL_EDGE: /* 0:1:1 */
+ au_writel(1<<irq_nr, IC0_CFG2CLR);
+ au_writel(1<<irq_nr, IC0_CFG1SET);
+ au_writel(1<<irq_nr, IC0_CFG0SET);
+ irq_desc[irq_nr].handler = &either_edge_irq_type;
+ break;
+ case INTC_INT_HIGH_LEVEL: /* 1:0:1 */
+ au_writel(1<<irq_nr, IC0_CFG2SET);
+ au_writel(1<<irq_nr, IC0_CFG1CLR);
+ au_writel(1<<irq_nr, IC0_CFG0SET);
+ irq_desc[irq_nr].handler = &level_irq_type;
+ break;
+ case INTC_INT_LOW_LEVEL: /* 1:1:0 */
+ au_writel(1<<irq_nr, IC0_CFG2SET);
+ au_writel(1<<irq_nr, IC0_CFG1SET);
+ au_writel(1<<irq_nr, IC0_CFG0CLR);
+ irq_desc[irq_nr].handler = &level_irq_type;
+ break;
+ case INTC_INT_DISABLED: /* 0:0:0 */
+ au_writel(1<<irq_nr, IC0_CFG0CLR);
+ au_writel(1<<irq_nr, IC0_CFG1CLR);
+ au_writel(1<<irq_nr, IC0_CFG2CLR);
+ break;
+ default: /* disable the interrupt */
+ printk("unexpected int type %d (irq %d)\n", type, irq_nr);
+ au_writel(1<<irq_nr, IC0_CFG0CLR);
+ au_writel(1<<irq_nr, IC0_CFG1CLR);
+ au_writel(1<<irq_nr, IC0_CFG2CLR);
+ return;
+ }
+ if (int_req) /* assign to interrupt request 1 */
+ au_writel(1<<irq_nr, IC0_ASSIGNCLR);
+ else /* assign to interrupt request 0 */
+ au_writel(1<<irq_nr, IC0_ASSIGNSET);
+ au_writel(1<<irq_nr, IC0_SRCSET);
+ au_writel(1<<irq_nr, IC0_MASKCLR);
+ au_writel(1<<irq_nr, IC0_WAKECLR);
+ }
+ au_sync();
+}
+
+
+void __init arch_init_irq(void)
+{
+ int i;
+ unsigned long cp0_status;
+ au1xxx_irq_map_t *imp;
+ extern au1xxx_irq_map_t au1xxx_irq_map[];
+ extern au1xxx_irq_map_t au1xxx_ic0_map[];
+ extern int au1xxx_nr_irqs;
+ extern int au1xxx_ic0_nr_irqs;
+
+ cp0_status = read_c0_status();
+ memset(irq_desc, 0, sizeof(irq_desc));
+ set_except_vector(0, au1000_IRQ);
+
+ /* Initialize interrupt controllers to a safe state.
+ */
+ au_writel(0xffffffff, IC0_CFG0CLR);
+ au_writel(0xffffffff, IC0_CFG1CLR);
+ au_writel(0xffffffff, IC0_CFG2CLR);
+ au_writel(0xffffffff, IC0_MASKCLR);
+ au_writel(0xffffffff, IC0_ASSIGNSET);
+ au_writel(0xffffffff, IC0_WAKECLR);
+ au_writel(0xffffffff, IC0_SRCSET);
+ au_writel(0xffffffff, IC0_FALLINGCLR);
+ au_writel(0xffffffff, IC0_RISINGCLR);
+ au_writel(0x00000000, IC0_TESTBIT);
+
+ au_writel(0xffffffff, IC1_CFG0CLR);
+ au_writel(0xffffffff, IC1_CFG1CLR);
+ au_writel(0xffffffff, IC1_CFG2CLR);
+ au_writel(0xffffffff, IC1_MASKCLR);
+ au_writel(0xffffffff, IC1_ASSIGNSET);
+ au_writel(0xffffffff, IC1_WAKECLR);
+ au_writel(0xffffffff, IC1_SRCSET);
+ au_writel(0xffffffff, IC1_FALLINGCLR);
+ au_writel(0xffffffff, IC1_RISINGCLR);
+ au_writel(0x00000000, IC1_TESTBIT);
+
+ /* Initialize IC0, which is fixed per processor.
+ */
+ imp = au1xxx_ic0_map;
+ for (i=0; i<au1xxx_ic0_nr_irqs; i++) {
+ setup_local_irq(imp->im_irq, imp->im_type, imp->im_request);
+ imp++;
+ }
+
+ /* Now set up the irq mapping for the board.
+ */
+ imp = au1xxx_irq_map;
+ for (i=0; i<au1xxx_nr_irqs; i++) {
+ setup_local_irq(imp->im_irq, imp->im_type, imp->im_request);
+ imp++;
+ }
+
+ set_c0_status(ALLINTS);
+
+ /* Board specific IRQ initialization.
+ */
+ if (board_init_irq)
+ (*board_init_irq)();
+}
+
+
+/*
+ * Interrupts are nested. Even if an interrupt handler is registered
+ * as "fast", we might get another interrupt before we return from
+ * intcX_reqX_irqdispatch().
+ */
+
+void intc0_req0_irqdispatch(struct pt_regs *regs)
+{
+ int irq = 0;
+ static unsigned long intc0_req0 = 0;
+
+ intc0_req0 |= au_readl(IC0_REQ0INT);
+
+ if (!intc0_req0) return;
+
+ /*
+ * Because of the tight timing of SETUP token to reply
+ * transactions, the USB devices-side packet complete
+ * interrupt needs the highest priority.
+ */
+ if ((intc0_req0 & (1<<AU1000_USB_DEV_REQ_INT))) {
+ intc0_req0 &= ~(1<<AU1000_USB_DEV_REQ_INT);
+ do_IRQ(AU1000_USB_DEV_REQ_INT, regs);
+ return;
+ }
+
+ irq = au_ffs(intc0_req0) - 1;
+ intc0_req0 &= ~(1<<irq);
+ do_IRQ(irq, regs);
+}
+
+
+void intc0_req1_irqdispatch(struct pt_regs *regs)
+{
+ int irq = 0;
+ static unsigned long intc0_req1 = 0;
+
+ intc0_req1 |= au_readl(IC0_REQ1INT);
+
+ if (!intc0_req1) return;
+
+ irq = au_ffs(intc0_req1) - 1;
+ intc0_req1 &= ~(1<<irq);
+#ifdef CONFIG_PM
+ if (irq == AU1000_TOY_MATCH2_INT) {
+ mask_and_ack_rise_edge_irq(irq);
+ counter0_irq(irq, NULL, regs);
+ local_enable_irq(irq);
+ }
+ else
+#endif
+ {
+ do_IRQ(irq, regs);
+ }
+}
+
+
+/*
+ * Interrupt Controller 1:
+ * interrupts 32 - 63
+ */
+void intc1_req0_irqdispatch(struct pt_regs *regs)
+{
+ int irq = 0;
+ static unsigned long intc1_req0 = 0;
+
+ intc1_req0 |= au_readl(IC1_REQ0INT);
+
+ if (!intc1_req0) return;
+
+ irq = au_ffs(intc1_req0) - 1;
+ intc1_req0 &= ~(1<<irq);
+ irq += 32;
+ do_IRQ(irq, regs);
+}
+
+
+void intc1_req1_irqdispatch(struct pt_regs *regs)
+{
+ int irq = 0;
+ static unsigned long intc1_req1 = 0;
+
+ intc1_req1 |= au_readl(IC1_REQ1INT);
+
+ if (!intc1_req1) return;
+
+ irq = au_ffs(intc1_req1) - 1;
+ intc1_req1 &= ~(1<<irq);
+ irq += 32;
+ do_IRQ(irq, regs);
+}
+
+#ifdef CONFIG_PM
+
+/* Save/restore the interrupt controller state.
+ * Called from the save/restore core registers as part of the
+ * au_sleep function in power.c.....maybe I should just pm_register()
+ * them instead?
+ */
+static uint sleep_intctl_config0[2];
+static uint sleep_intctl_config1[2];
+static uint sleep_intctl_config2[2];
+static uint sleep_intctl_src[2];
+static uint sleep_intctl_assign[2];
+static uint sleep_intctl_wake[2];
+static uint sleep_intctl_mask[2];
+
+void
+save_au1xxx_intctl(void)
+{
+ sleep_intctl_config0[0] = au_readl(IC0_CFG0RD);
+ sleep_intctl_config1[0] = au_readl(IC0_CFG1RD);
+ sleep_intctl_config2[0] = au_readl(IC0_CFG2RD);
+ sleep_intctl_src[0] = au_readl(IC0_SRCRD);
+ sleep_intctl_assign[0] = au_readl(IC0_ASSIGNRD);
+ sleep_intctl_wake[0] = au_readl(IC0_WAKERD);
+ sleep_intctl_mask[0] = au_readl(IC0_MASKRD);
+
+ sleep_intctl_config0[1] = au_readl(IC1_CFG0RD);
+ sleep_intctl_config1[1] = au_readl(IC1_CFG1RD);
+ sleep_intctl_config2[1] = au_readl(IC1_CFG2RD);
+ sleep_intctl_src[1] = au_readl(IC1_SRCRD);
+ sleep_intctl_assign[1] = au_readl(IC1_ASSIGNRD);
+ sleep_intctl_wake[1] = au_readl(IC1_WAKERD);
+ sleep_intctl_mask[1] = au_readl(IC1_MASKRD);
+}
+
+/* For most restore operations, we clear the entire register and
+ * then set the bits we found during the save.
+ */
+void
+restore_au1xxx_intctl(void)
+{
+ au_writel(0xffffffff, IC0_MASKCLR); au_sync();
+
+ au_writel(0xffffffff, IC0_CFG0CLR); au_sync();
+ au_writel(sleep_intctl_config0[0], IC0_CFG0SET); au_sync();
+ au_writel(0xffffffff, IC0_CFG1CLR); au_sync();
+ au_writel(sleep_intctl_config1[0], IC0_CFG1SET); au_sync();
+ au_writel(0xffffffff, IC0_CFG2CLR); au_sync();
+ au_writel(sleep_intctl_config2[0], IC0_CFG2SET); au_sync();
+ au_writel(0xffffffff, IC0_SRCCLR); au_sync();
+ au_writel(sleep_intctl_src[0], IC0_SRCSET); au_sync();
+ au_writel(0xffffffff, IC0_ASSIGNCLR); au_sync();
+ au_writel(sleep_intctl_assign[0], IC0_ASSIGNSET); au_sync();
+ au_writel(0xffffffff, IC0_WAKECLR); au_sync();
+ au_writel(sleep_intctl_wake[0], IC0_WAKESET); au_sync();
+ au_writel(0xffffffff, IC0_RISINGCLR); au_sync();
+ au_writel(0xffffffff, IC0_FALLINGCLR); au_sync();
+ au_writel(0x00000000, IC0_TESTBIT); au_sync();
+
+ au_writel(0xffffffff, IC1_MASKCLR); au_sync();
+
+ au_writel(0xffffffff, IC1_CFG0CLR); au_sync();
+ au_writel(sleep_intctl_config0[1], IC1_CFG0SET); au_sync();
+ au_writel(0xffffffff, IC1_CFG1CLR); au_sync();
+ au_writel(sleep_intctl_config1[1], IC1_CFG1SET); au_sync();
+ au_writel(0xffffffff, IC1_CFG2CLR); au_sync();
+ au_writel(sleep_intctl_config2[1], IC1_CFG2SET); au_sync();
+ au_writel(0xffffffff, IC1_SRCCLR); au_sync();
+ au_writel(sleep_intctl_src[1], IC1_SRCSET); au_sync();
+ au_writel(0xffffffff, IC1_ASSIGNCLR); au_sync();
+ au_writel(sleep_intctl_assign[1], IC1_ASSIGNSET); au_sync();
+ au_writel(0xffffffff, IC1_WAKECLR); au_sync();
+ au_writel(sleep_intctl_wake[1], IC1_WAKESET); au_sync();
+ au_writel(0xffffffff, IC1_RISINGCLR); au_sync();
+ au_writel(0xffffffff, IC1_FALLINGCLR); au_sync();
+ au_writel(0x00000000, IC1_TESTBIT); au_sync();
+
+ au_writel(sleep_intctl_mask[1], IC1_MASKSET); au_sync();
+
+ au_writel(sleep_intctl_mask[0], IC0_MASKSET); au_sync();
+}
+#endif /* CONFIG_PM */
diff --git a/arch/mips/au1000/common/pci.c b/arch/mips/au1000/common/pci.c
new file mode 100644
index 00000000000..533721eef6a
--- /dev/null
+++ b/arch/mips/au1000/common/pci.c
@@ -0,0 +1,97 @@
+/*
+ * BRIEF MODULE DESCRIPTION
+ * Alchemy/AMD Au1x00 pci support.
+ *
+ * Copyright 2001,2002,2003 MontaVista Software Inc.
+ * Author: MontaVista Software, Inc.
+ * ppopov@mvista.com or source@mvista.com
+ *
+ * Copyright (C) 2004 by Ralf Baechle (ralf@linux-mips.org)
+ *
+ * Support for all devices (greater than 16) added by David Gathright.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#include <linux/config.h>
+#include <linux/types.h>
+#include <linux/pci.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+
+#include <asm/mach-au1x00/au1000.h>
+
+/* TBD */
+static struct resource pci_io_resource = {
+ "pci IO space",
+ (u32)PCI_IO_START,
+ (u32)PCI_IO_END,
+ IORESOURCE_IO
+};
+
+static struct resource pci_mem_resource = {
+ "pci memory space",
+ (u32)PCI_MEM_START,
+ (u32)PCI_MEM_END,
+ IORESOURCE_MEM
+};
+
+extern struct pci_ops au1x_pci_ops;
+
+static struct pci_controller au1x_controller = {
+ .pci_ops = &au1x_pci_ops,
+ .io_resource = &pci_io_resource,
+ .mem_resource = &pci_mem_resource,
+};
+
+#if defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550)
+static unsigned long virt_io_addr;
+#endif
+
+static int __init au1x_pci_setup(void)
+{
+#if defined(CONFIG_SOC_AU1500) || defined(CONFIG_SOC_AU1550)
+ virt_io_addr = (unsigned long)ioremap(Au1500_PCI_IO_START,
+ Au1500_PCI_IO_END - Au1500_PCI_IO_START + 1);
+
+ if (!virt_io_addr) {
+ printk(KERN_ERR "Unable to ioremap pci space\n");
+ return 1;
+ }
+
+#ifdef CONFIG_DMA_NONCOHERENT
+ /*
+ * Set the NC bit in controller for Au1500 pre-AC silicon
+ */
+ u32 prid = read_c0_prid();
+ if ( (prid & 0xFF000000) == 0x01000000 && prid < 0x01030202) {
+ au_writel( 1<<16 | au_readl(Au1500_PCI_CFG), Au1500_PCI_CFG);
+ printk("Non-coherent PCI accesses enabled\n");
+ }
+#endif
+
+ set_io_port_base(virt_io_addr);
+#endif
+
+ register_pci_controller(&au1x_controller);
+ return 0;
+}
+
+arch_initcall(au1x_pci_setup);
diff --git a/arch/mips/au1000/common/platform.c b/arch/mips/au1000/common/platform.c
new file mode 100644
index 00000000000..0776b2db564
--- /dev/null
+++ b/arch/mips/au1000/common/platform.c
@@ -0,0 +1,53 @@
+/*
+ * Platform device support for Au1x00 SoCs.
+ *
+ * Copyright 2004, Matt Porter <mporter@kernel.crashing.org>
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2. This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+#include <linux/device.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/resource.h>
+
+#include <asm/mach-au1x00/au1000.h>
+
+static struct resource au1xxx_usb_ohci_resources[] = {
+ [0] = {
+ .start = USB_OHCI_BASE,
+ .end = USB_OHCI_BASE + USB_OHCI_LEN,
+ .flags = IORESOURCE_MEM,
+ },
+ [1] = {
+ .start = AU1000_USB_HOST_INT,
+ .end = AU1000_USB_HOST_INT,
+ .flags = IORESOURCE_IRQ,
+ },
+};
+
+/* The dmamask must be set for OHCI to work */
+static u64 ohci_dmamask = ~(u32)0;
+
+static struct platform_device au1xxx_usb_ohci_device = {
+ .name = "au1xxx-ohci",
+ .id = 0,
+ .dev = {
+ .dma_mask = &ohci_dmamask,
+ .coherent_dma_mask = 0xffffffff,
+ },
+ .num_resources = ARRAY_SIZE(au1xxx_usb_ohci_resources),
+ .resource = au1xxx_usb_ohci_resources,
+};
+
+static struct platform_device *au1xxx_platform_devices[] __initdata = {
+ &au1xxx_usb_ohci_device,
+};
+
+int au1xxx_platform_init(void)
+{
+ return platform_add_devices(au1xxx_platform_devices, ARRAY_SIZE(au1xxx_platform_devices));
+}
+
+arch_initcall(au1xxx_platform_init);
diff --git a/arch/mips/au1000/common/power.c b/arch/mips/au1000/common/power.c
new file mode 100644
index 00000000000..c40daccbb5b
--- /dev/null
+++ b/arch/mips/au1000/common/power.c
@@ -0,0 +1,493 @@
+/*
+ * BRIEF MODULE DESCRIPTION
+ * Au1000 Power Management routines.
+ *
+ * Copyright 2001 MontaVista Software Inc.
+ * Author: MontaVista Software, Inc.
+ * ppopov@mvista.com or source@mvista.com
+ *
+ * Some of the routines are right out of init/main.c, whose
+ * copyrights apply here.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#include <linux/config.h>
+#include <linux/init.h>
+#include <linux/pm.h>
+#include <linux/slab.h>
+#include <linux/sysctl.h>
+
+#include <asm/string.h>
+#include <asm/uaccess.h>
+#include <asm/io.h>
+#include <asm/system.h>
+#include <asm/mach-au1x00/au1000.h>
+
+#ifdef CONFIG_PM
+
+#define DEBUG 1
+#ifdef DEBUG
+# define DPRINTK(fmt, args...) printk("%s: " fmt, __FUNCTION__ , ## args)
+#else
+# define DPRINTK(fmt, args...)
+#endif
+
+static void calibrate_delay(void);
+
+extern void set_au1x00_speed(unsigned int new_freq);
+extern unsigned int get_au1x00_speed(void);
+extern unsigned long get_au1x00_uart_baud_base(void);
+extern void set_au1x00_uart_baud_base(unsigned long new_baud_base);
+extern unsigned long save_local_and_disable(int controller);
+extern void restore_local_and_enable(int controller, unsigned long mask);
+extern void local_enable_irq(unsigned int irq_nr);
+
+/* Quick acpi hack. This will have to change! */
+#define CTL_ACPI 9999
+#define ACPI_S1_SLP_TYP 19
+#define ACPI_SLEEP 21
+
+
+static DEFINE_SPINLOCK(pm_lock);
+
+/* We need to save/restore a bunch of core registers that are
+ * either volatile or reset to some state across a processor sleep.
+ * If reading a register doesn't provide a proper result for a
+ * later restore, we have to provide a function for loading that
+ * register and save a copy.
+ *
+ * We only have to save/restore registers that aren't otherwise
+ * done as part of a driver pm_* function.
+ */
+static uint sleep_aux_pll_cntrl;
+static uint sleep_cpu_pll_cntrl;
+static uint sleep_pin_function;
+static uint sleep_uart0_inten;
+static uint sleep_uart0_fifoctl;
+static uint sleep_uart0_linectl;
+static uint sleep_uart0_clkdiv;
+static uint sleep_uart0_enable;
+static uint sleep_usbhost_enable;
+static uint sleep_usbdev_enable;
+static uint sleep_static_memctlr[4][3];
+
+/* Define this to cause the value you write to /proc/sys/pm/sleep to
+ * set the TOY timer for the amount of time you want to sleep.
+ * This is done mainly for testing, but may be useful in other cases.
+ * The value is number of 32KHz ticks to sleep.
+ */
+#define SLEEP_TEST_TIMEOUT 1
+#ifdef SLEEP_TEST_TIMEOUT
+static int sleep_ticks;
+void wakeup_counter0_set(int ticks);
+#endif
+
+static void
+save_core_regs(void)
+{
+ extern void save_au1xxx_intctl(void);
+ extern void pm_eth0_shutdown(void);
+
+ /* Do the serial ports.....these really should be a pm_*
+ * registered function by the driver......but of course the
+ * standard serial driver doesn't understand our Au1xxx
+ * unique registers.
+ */
+ sleep_uart0_inten = au_readl(UART0_ADDR + UART_IER);
+ sleep_uart0_fifoctl = au_readl(UART0_ADDR + UART_FCR);
+ sleep_uart0_linectl = au_readl(UART0_ADDR + UART_LCR);
+ sleep_uart0_clkdiv = au_readl(UART0_ADDR + UART_CLK);
+ sleep_uart0_enable = au_readl(UART0_ADDR + UART_MOD_CNTRL);
+
+ /* Shutdown USB host/device.
+ */
+ sleep_usbhost_enable = au_readl(USB_HOST_CONFIG);
+
+ /* There appears to be some undocumented reset register....
+ */
+ au_writel(0, 0xb0100004); au_sync();
+ au_writel(0, USB_HOST_CONFIG); au_sync();
+
+ sleep_usbdev_enable = au_readl(USBD_ENABLE);
+ au_writel(0, USBD_ENABLE); au_sync();
+
+ /* Save interrupt controller state.
+ */
+ save_au1xxx_intctl();
+
+ /* Clocks and PLLs.
+ */
+ sleep_aux_pll_cntrl = au_readl(SYS_AUXPLL);
+
+ /* We don't really need to do this one, but unless we
+ * write it again it won't have a valid value if we
+ * happen to read it.
+ */
+ sleep_cpu_pll_cntrl = au_readl(SYS_CPUPLL);
+
+ sleep_pin_function = au_readl(SYS_PINFUNC);
+
+ /* Save the static memory controller configuration.
+ */
+ sleep_static_memctlr[0][0] = au_readl(MEM_STCFG0);
+ sleep_static_memctlr[0][1] = au_readl(MEM_STTIME0);
+ sleep_static_memctlr[0][2] = au_readl(MEM_STADDR0);
+ sleep_static_memctlr[1][0] = au_readl(MEM_STCFG1);
+ sleep_static_memctlr[1][1] = au_readl(MEM_STTIME1);
+ sleep_static_memctlr[1][2] = au_readl(MEM_STADDR1);
+ sleep_static_memctlr[2][0] = au_readl(MEM_STCFG2);
+ sleep_static_memctlr[2][1] = au_readl(MEM_STTIME2);
+ sleep_static_memctlr[2][2] = au_readl(MEM_STADDR2);
+ sleep_static_memctlr[3][0] = au_readl(MEM_STCFG3);
+ sleep_static_memctlr[3][1] = au_readl(MEM_STTIME3);
+ sleep_static_memctlr[3][2] = au_readl(MEM_STADDR3);
+}
+
+static void
+restore_core_regs(void)
+{
+ extern void restore_au1xxx_intctl(void);
+ extern void wakeup_counter0_adjust(void);
+
+ au_writel(sleep_aux_pll_cntrl, SYS_AUXPLL); au_sync();
+ au_writel(sleep_cpu_pll_cntrl, SYS_CPUPLL); au_sync();
+ au_writel(sleep_pin_function, SYS_PINFUNC); au_sync();
+
+ /* Restore the static memory controller configuration.
+ */
+ au_writel(sleep_static_memctlr[0][0], MEM_STCFG0);
+ au_writel(sleep_static_memctlr[0][1], MEM_STTIME0);
+ au_writel(sleep_static_memctlr[0][2], MEM_STADDR0);
+ au_writel(sleep_static_memctlr[1][0], MEM_STCFG1);
+ au_writel(sleep_static_memctlr[1][1], MEM_STTIME1);
+ au_writel(sleep_static_memctlr[1][2], MEM_STADDR1);
+ au_writel(sleep_static_memctlr[2][0], MEM_STCFG2);
+ au_writel(sleep_static_memctlr[2][1], MEM_STTIME2);
+ au_writel(sleep_static_memctlr[2][2], MEM_STADDR2);
+ au_writel(sleep_static_memctlr[3][0], MEM_STCFG3);
+ au_writel(sleep_static_memctlr[3][1], MEM_STTIME3);
+ au_writel(sleep_static_memctlr[3][2], MEM_STADDR3);
+
+ /* Enable the UART if it was enabled before sleep.
+ * I guess I should define module control bits........
+ */
+ if (sleep_uart0_enable & 0x02) {
+ au_writel(0, UART0_ADDR + UART_MOD_CNTRL); au_sync();
+ au_writel(1, UART0_ADDR + UART_MOD_CNTRL); au_sync();
+ au_writel(3, UART0_ADDR + UART_MOD_CNTRL); au_sync();
+ au_writel(sleep_uart0_inten, UART0_ADDR + UART_IER); au_sync();
+ au_writel(sleep_uart0_fifoctl, UART0_ADDR + UART_FCR); au_sync();
+ au_writel(sleep_uart0_linectl, UART0_ADDR + UART_LCR); au_sync();
+ au_writel(sleep_uart0_clkdiv, UART0_ADDR + UART_CLK); au_sync();
+ }
+
+ restore_au1xxx_intctl();
+ wakeup_counter0_adjust();
+}
+
+unsigned long suspend_mode;
+
+void wakeup_from_suspend(void)
+{
+ suspend_mode = 0;
+}
+
+int au_sleep(void)
+{
+ unsigned long wakeup, flags;
+ extern void save_and_sleep(void);
+
+ spin_lock_irqsave(&pm_lock,flags);
+
+ save_core_regs();
+
+ flush_cache_all();
+
+ /** The code below is all system dependent and we should probably
+ ** have a function call out of here to set this up. You need
+ ** to configure the GPIO or timer interrupts that will bring
+ ** you out of sleep.
+ ** For testing, the TOY counter wakeup is useful.
+ **/
+
+#if 0
+ au_writel(au_readl(SYS_PINSTATERD) & ~(1 << 11), SYS_PINSTATERD);
+
+ /* gpio 6 can cause a wake up event */
+ wakeup = au_readl(SYS_WAKEMSK);
+ wakeup &= ~(1 << 8); /* turn off match20 wakeup */
+ wakeup |= 1 << 6; /* turn on gpio 6 wakeup */
+#else
+ /* For testing, allow match20 to wake us up.
+ */
+#ifdef SLEEP_TEST_TIMEOUT
+ wakeup_counter0_set(sleep_ticks);
+#endif
+ wakeup = 1 << 8; /* turn on match20 wakeup */
+ wakeup = 0;
+#endif
+ au_writel(1, SYS_WAKESRC); /* clear cause */
+ au_sync();
+ au_writel(wakeup, SYS_WAKEMSK);
+ au_sync();
+
+ save_and_sleep();
+
+ /* after a wakeup, the cpu vectors back to 0x1fc00000 so
+ * it's up to the boot code to get us back here.
+ */
+ restore_core_regs();
+ spin_unlock_irqrestore(&pm_lock, flags);
+ return 0;
+}
+
+static int pm_do_sleep(ctl_table * ctl, int write, struct file *file,
+ void *buffer, size_t * len)
+{
+ int retval = 0;
+#ifdef SLEEP_TEST_TIMEOUT
+#define TMPBUFLEN2 16
+ char buf[TMPBUFLEN2], *p;
+#endif
+
+ if (!write) {
+ *len = 0;
+ } else {
+#ifdef SLEEP_TEST_TIMEOUT
+ if (*len > TMPBUFLEN2 - 1) {
+ return -EFAULT;
+ }
+ if (copy_from_user(buf, buffer, *len)) {
+ return -EFAULT;
+ }
+ buf[*len] = 0;
+ p = buf;
+ sleep_ticks = simple_strtoul(p, &p, 0);
+#endif
+ retval = pm_send_all(PM_SUSPEND, (void *) 2);
+
+ if (retval)
+ return retval;
+
+ au_sleep();
+ retval = pm_send_all(PM_RESUME, (void *) 0);
+ }
+ return retval;
+}
+
+static int pm_do_suspend(ctl_table * ctl, int write, struct file *file,
+ void *buffer, size_t * len)
+{
+ int retval = 0;
+ void au1k_wait(void);
+
+ if (!write) {
+ *len = 0;
+ } else {
+ retval = pm_send_all(PM_SUSPEND, (void *) 2);
+ if (retval)
+ return retval;
+ suspend_mode = 1;
+ au1k_wait();
+ retval = pm_send_all(PM_RESUME, (void *) 0);
+ }
+ return retval;
+}
+
+
+static int pm_do_freq(ctl_table * ctl, int write, struct file *file,
+ void *buffer, size_t * len)
+{
+ int retval = 0, i;
+ unsigned long val, pll;
+#define TMPBUFLEN 64
+#define MAX_CPU_FREQ 396
+ char buf[TMPBUFLEN], *p;
+ unsigned long flags, intc0_mask, intc1_mask;
+ unsigned long old_baud_base, old_cpu_freq, baud_rate, old_clk,
+ old_refresh;
+ unsigned long new_baud_base, new_cpu_freq, new_clk, new_refresh;
+
+ spin_lock_irqsave(&pm_lock, flags);
+ if (!write) {
+ *len = 0;
+ } else {
+ /* Parse the new frequency */
+ if (*len > TMPBUFLEN - 1) {
+ spin_unlock_irqrestore(&pm_lock, flags);
+ return -EFAULT;
+ }
+ if (copy_from_user(buf, buffer, *len)) {
+ spin_unlock_irqrestore(&pm_lock, flags);
+ return -EFAULT;
+ }
+ buf[*len] = 0;
+ p = buf;
+ val = simple_strtoul(p, &p, 0);
+ if (val > MAX_CPU_FREQ) {
+ spin_unlock_irqrestore(&pm_lock, flags);
+ return -EFAULT;
+ }
+
+ pll = val / 12;
+ if ((pll > 33) || (pll < 7)) { /* 396 MHz max, 84 MHz min */
+ /* revisit this for higher speed cpus */
+ spin_unlock_irqrestore(&pm_lock, flags);
+ return -EFAULT;
+ }
+
+ old_baud_base = get_au1x00_uart_baud_base();
+ old_cpu_freq = get_au1x00_speed();
+
+ new_cpu_freq = pll * 12 * 1000000;
+ new_baud_base = (new_cpu_freq / (2 * ((int)(au_readl(SYS_POWERCTRL)&0x03) + 2) * 16));
+ set_au1x00_speed(new_cpu_freq);
+ set_au1x00_uart_baud_base(new_baud_base);
+
+ old_refresh = au_readl(MEM_SDREFCFG) & 0x1ffffff;
+ new_refresh =
+ ((old_refresh * new_cpu_freq) /
+ old_cpu_freq) | (au_readl(MEM_SDREFCFG) & ~0x1ffffff);
+
+ au_writel(pll, SYS_CPUPLL);
+ au_sync_delay(1);
+ au_writel(new_refresh, MEM_SDREFCFG);
+ au_sync_delay(1);
+
+ for (i = 0; i < 4; i++) {
+ if (au_readl
+ (UART_BASE + UART_MOD_CNTRL +
+ i * 0x00100000) == 3) {
+ old_clk =
+ au_readl(UART_BASE + UART_CLK +
+ i * 0x00100000);
+ // baud_rate = baud_base/clk
+ baud_rate = old_baud_base / old_clk;
+ /* we won't get an exact baud rate and the error
+ * could be significant enough that our new
+ * calculation will result in a clock that will
+ * give us a baud rate that's too far off from
+ * what we really want.
+ */
+ if (baud_rate > 100000)
+ baud_rate = 115200;
+ else if (baud_rate > 50000)
+ baud_rate = 57600;
+ else if (baud_rate > 30000)
+ baud_rate = 38400;
+ else if (baud_rate > 17000)
+ baud_rate = 19200;
+ else
+ (baud_rate = 9600);
+ // new_clk = new_baud_base/baud_rate
+ new_clk = new_baud_base / baud_rate;
+ au_writel(new_clk,
+ UART_BASE + UART_CLK +
+ i * 0x00100000);
+ au_sync_delay(10);
+ }
+ }
+ }
+
+
+ /* We don't want _any_ interrupts other than
+ * match20. Otherwise our calibrate_delay()
+ * calculation will be off, potentially a lot.
+ */
+ intc0_mask = save_local_and_disable(0);
+ intc1_mask = save_local_and_disable(1);
+ local_enable_irq(AU1000_TOY_MATCH2_INT);
+ spin_unlock_irqrestore(&pm_lock, flags);
+ calibrate_delay();
+ restore_local_and_enable(0, intc0_mask);
+ restore_local_and_enable(1, intc1_mask);
+ return retval;
+}
+
+
+static struct ctl_table pm_table[] = {
+ {ACPI_S1_SLP_TYP, "suspend", NULL, 0, 0600, NULL, &pm_do_suspend},
+ {ACPI_SLEEP, "sleep", NULL, 0, 0600, NULL, &pm_do_sleep},
+ {CTL_ACPI, "freq", NULL, 0, 0600, NULL, &pm_do_freq},
+ {0}
+};
+
+static struct ctl_table pm_dir_table[] = {
+ {CTL_ACPI, "pm", NULL, 0, 0555, pm_table},
+ {0}
+};
+
+/*
+ * Initialize power interface
+ */
+static int __init pm_init(void)
+{
+ register_sysctl_table(pm_dir_table, 1);
+ return 0;
+}
+
+__initcall(pm_init);
+
+
+/*
+ * This is right out of init/main.c
+ */
+
+/* This is the number of bits of precision for the loops_per_jiffy. Each
+ bit takes on average 1.5/HZ seconds. This (like the original) is a little
+ better than 1% */
+#define LPS_PREC 8
+
+static void calibrate_delay(void)
+{
+ unsigned long ticks, loopbit;
+ int lps_precision = LPS_PREC;
+
+ loops_per_jiffy = (1 << 12);
+
+ while (loops_per_jiffy <<= 1) {
+ /* wait for "start of" clock tick */
+ ticks = jiffies;
+ while (ticks == jiffies)
+ /* nothing */ ;
+ /* Go .. */
+ ticks = jiffies;
+ __delay(loops_per_jiffy);
+ ticks = jiffies - ticks;
+ if (ticks)
+ break;
+ }
+
+/* Do a binary approximation to get loops_per_jiffy set to equal one clock
+ (up to lps_precision bits) */
+ loops_per_jiffy >>= 1;
+ loopbit = loops_per_jiffy;
+ while (lps_precision-- && (loopbit >>= 1)) {
+ loops_per_jiffy |= loopbit;
+ ticks = jiffies;
+ while (ticks == jiffies);
+ ticks = jiffies;
+ __delay(loops_per_jiffy);
+ if (jiffies != ticks) /* longer than 1 tick */
+ loops_per_jiffy &= ~loopbit;
+ }
+}
+#endif /* CONFIG_PM */
diff --git a/arch/mips/au1000/common/prom.c b/arch/mips/au1000/common/prom.c
new file mode 100644
index 00000000000..22e5a85af4d
--- /dev/null
+++ b/arch/mips/au1000/common/prom.c
@@ -0,0 +1,162 @@
+/*
+ *
+ * BRIEF MODULE DESCRIPTION
+ * PROM library initialisation code, assuming a version of
+ * pmon is the boot code.
+ *
+ * Copyright 2000,2001 MontaVista Software Inc.
+ * Author: MontaVista Software, Inc.
+ * ppopov@mvista.com or source@mvista.com
+ *
+ * This file was derived from Carsten Langgaard's
+ * arch/mips/mips-boards/xx files.
+ *
+ * Carsten Langgaard, carstenl@mips.com
+ * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <linux/module.h>
+#include <linux/kernel.h>
+#include <linux/init.h>
+#include <linux/string.h>
+
+#include <asm/bootinfo.h>
+
+/* #define DEBUG_CMDLINE */
+
+extern int prom_argc;
+extern char **prom_argv, **prom_envp;
+
+typedef struct
+{
+ char *name;
+/* char *val; */
+}t_env_var;
+
+
+char * prom_getcmdline(void)
+{
+ return &(arcs_cmdline[0]);
+}
+
+void prom_init_cmdline(void)
+{
+ char *cp;
+ int actr;
+
+ actr = 1; /* Always ignore argv[0] */
+
+ cp = &(arcs_cmdline[0]);
+ while(actr < prom_argc) {
+ strcpy(cp, prom_argv[actr]);
+ cp += strlen(prom_argv[actr]);
+ *cp++ = ' ';
+ actr++;
+ }
+ if (cp != &(arcs_cmdline[0])) /* get rid of trailing space */
+ --cp;
+ *cp = '\0';
+
+}
+
+
+char *prom_getenv(char *envname)
+{
+ /*
+ * Return a pointer to the given environment variable.
+ * Environment variables are stored in the form of "memsize=64".
+ */
+
+ t_env_var *env = (t_env_var *)prom_envp;
+ int i;
+
+ i = strlen(envname);
+
+ while(env->name) {
+ if(strncmp(envname, env->name, i) == 0) {
+ return(env->name + strlen(envname) + 1);
+ }
+ env++;
+ }
+ return(NULL);
+}
+
+inline unsigned char str2hexnum(unsigned char c)
+{
+ if(c >= '0' && c <= '9')
+ return c - '0';
+ if(c >= 'a' && c <= 'f')
+ return c - 'a' + 10;
+ if(c >= 'A' && c <= 'F')
+ return c - 'A' + 10;
+ return 0; /* foo */
+}
+
+inline void str2eaddr(unsigned char *ea, unsigned char *str)
+{
+ int i;
+
+ for(i = 0; i < 6; i++) {
+ unsigned char num;
+
+ if((*str == '.') || (*str == ':'))
+ str++;
+ num = str2hexnum(*str++) << 4;
+ num |= (str2hexnum(*str++));
+ ea[i] = num;
+ }
+}
+
+int get_ethernet_addr(char *ethernet_addr)
+{
+ char *ethaddr_str;
+
+ ethaddr_str = prom_getenv("ethaddr");
+ if (!ethaddr_str) {
+ printk("ethaddr not set in boot prom\n");
+ return -1;
+ }
+ str2eaddr(ethernet_addr, ethaddr_str);
+
+#if 0
+ {
+ int i;
+
+ printk("get_ethernet_addr: ");
+ for (i=0; i<5; i++)
+ printk("%02x:", (unsigned char)*(ethernet_addr+i));
+ printk("%02x\n", *(ethernet_addr+i));
+ }
+#endif
+
+ return 0;
+}
+
+unsigned long __init prom_free_prom_memory(void)
+{
+ return 0;
+}
+
+EXPORT_SYMBOL(prom_getcmdline);
+EXPORT_SYMBOL(get_ethernet_addr);
+EXPORT_SYMBOL(str2eaddr);
diff --git a/arch/mips/au1000/common/puts.c b/arch/mips/au1000/common/puts.c
new file mode 100644
index 00000000000..c2ae4624b77
--- /dev/null
+++ b/arch/mips/au1000/common/puts.c
@@ -0,0 +1,145 @@
+/*
+ *
+ * BRIEF MODULE DESCRIPTION
+ * Low level uart routines to directly access a 16550 uart.
+ *
+ * Copyright 2001 MontaVista Software Inc.
+ * Author: MontaVista Software, Inc.
+ * ppopov@mvista.com or source@mvista.com
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+
+#include <linux/types.h>
+#include <asm/mach-au1x00/au1000.h>
+
+#define SERIAL_BASE UART_BASE
+#define SER_CMD 0x7
+#define SER_DATA 0x1
+#define TX_BUSY 0x20
+
+#define TIMEOUT 0xffffff
+#define SLOW_DOWN
+
+static const char digits[16] = "0123456789abcdef";
+static volatile unsigned long * const com1 = (unsigned long *)SERIAL_BASE;
+
+
+#ifdef SLOW_DOWN
+static inline void slow_down(void)
+{
+ int k;
+ for (k=0; k<10000; k++);
+}
+#else
+#define slow_down()
+#endif
+
+void
+putch(const unsigned char c)
+{
+ unsigned char ch;
+ int i = 0;
+
+ do {
+ ch = com1[SER_CMD];
+ slow_down();
+ i++;
+ if (i>TIMEOUT) {
+ break;
+ }
+ } while (0 == (ch & TX_BUSY));
+ com1[SER_DATA] = c;
+}
+
+void
+puts(unsigned char *cp)
+{
+ unsigned char ch;
+ int i = 0;
+
+ while (*cp) {
+ do {
+ ch = com1[SER_CMD];
+ slow_down();
+ i++;
+ if (i>TIMEOUT) {
+ break;
+ }
+ } while (0 == (ch & TX_BUSY));
+ com1[SER_DATA] = *cp++;
+ }
+ putch('\r');
+ putch('\n');
+}
+
+void
+fputs(const char *cp)
+{
+ unsigned char ch;
+ int i = 0;
+
+ while (*cp) {
+
+ do {
+ ch = com1[SER_CMD];
+ slow_down();
+ i++;
+ if (i>TIMEOUT) {
+ break;
+ }
+ } while (0 == (ch & TX_BUSY));
+ com1[SER_DATA] = *cp++;
+ }
+}
+
+
+void
+put64(uint64_t ul)
+{
+ int cnt;
+ unsigned ch;
+
+ cnt = 16; /* 16 nibbles in a 64 bit long */
+ putch('0');
+ putch('x');
+ do {
+ cnt--;
+ ch = (unsigned char)(ul >> cnt * 4) & 0x0F;
+ putch(digits[ch]);
+ } while (cnt > 0);
+}
+
+void
+put32(unsigned u)
+{
+ int cnt;
+ unsigned ch;
+
+ cnt = 8; /* 8 nibbles in a 32 bit long */
+ putch('0');
+ putch('x');
+ do {
+ cnt--;
+ ch = (unsigned char)(u >> cnt * 4) & 0x0F;
+ putch(digits[ch]);
+ } while (cnt > 0);
+}
diff --git a/arch/mips/au1000/common/reset.c b/arch/mips/au1000/common/reset.c
new file mode 100644
index 00000000000..65b84db800e
--- /dev/null
+++ b/arch/mips/au1000/common/reset.c
@@ -0,0 +1,195 @@
+/*
+ *
+ * BRIEF MODULE DESCRIPTION
+ * Au1000 reset routines.
+ *
+ * Copyright 2001 MontaVista Software Inc.
+ * Author: MontaVista Software, Inc.
+ * ppopov@mvista.com or source@mvista.com
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#include <linux/config.h>
+#include <linux/sched.h>
+#include <linux/mm.h>
+#include <asm/io.h>
+#include <asm/pgtable.h>
+#include <asm/processor.h>
+#include <asm/reboot.h>
+#include <asm/system.h>
+#include <asm/mach-au1x00/au1000.h>
+
+extern int au_sleep(void);
+extern void (*flush_cache_all)(void);
+
+void au1000_restart(char *command)
+{
+ /* Set all integrated peripherals to disabled states */
+ extern void board_reset (void);
+ u32 prid = read_c0_prid();
+
+ printk(KERN_NOTICE "\n** Resetting Integrated Peripherals\n");
+ switch (prid & 0xFF000000)
+ {
+ case 0x00000000: /* Au1000 */
+ au_writel(0x02, 0xb0000010); /* ac97_enable */
+ au_writel(0x08, 0xb017fffc); /* usbh_enable - early errata */
+ asm("sync");
+ au_writel(0x00, 0xb017fffc); /* usbh_enable */
+ au_writel(0x00, 0xb0200058); /* usbd_enable */
+ au_writel(0x00, 0xb0300040); /* ir_enable */
+ au_writel(0x00, 0xb4004104); /* mac dma */
+ au_writel(0x00, 0xb4004114); /* mac dma */
+ au_writel(0x00, 0xb4004124); /* mac dma */
+ au_writel(0x00, 0xb4004134); /* mac dma */
+ au_writel(0x00, 0xb0520000); /* macen0 */
+ au_writel(0x00, 0xb0520004); /* macen1 */
+ au_writel(0x00, 0xb1000008); /* i2s_enable */
+ au_writel(0x00, 0xb1100100); /* uart0_enable */
+ au_writel(0x00, 0xb1200100); /* uart1_enable */
+ au_writel(0x00, 0xb1300100); /* uart2_enable */
+ au_writel(0x00, 0xb1400100); /* uart3_enable */
+ au_writel(0x02, 0xb1600100); /* ssi0_enable */
+ au_writel(0x02, 0xb1680100); /* ssi1_enable */
+ au_writel(0x00, 0xb1900020); /* sys_freqctrl0 */
+ au_writel(0x00, 0xb1900024); /* sys_freqctrl1 */
+ au_writel(0x00, 0xb1900028); /* sys_clksrc */
+ au_writel(0x10, 0xb1900060); /* sys_cpupll */
+ au_writel(0x00, 0xb1900064); /* sys_auxpll */
+ au_writel(0x00, 0xb1900100); /* sys_pininputen */
+ break;
+ case 0x01000000: /* Au1500 */
+ au_writel(0x02, 0xb0000010); /* ac97_enable */
+ au_writel(0x08, 0xb017fffc); /* usbh_enable - early errata */
+ asm("sync");
+ au_writel(0x00, 0xb017fffc); /* usbh_enable */
+ au_writel(0x00, 0xb0200058); /* usbd_enable */
+ au_writel(0x00, 0xb4004104); /* mac dma */
+ au_writel(0x00, 0xb4004114); /* mac dma */
+ au_writel(0x00, 0xb4004124); /* mac dma */
+ au_writel(0x00, 0xb4004134); /* mac dma */
+ au_writel(0x00, 0xb1520000); /* macen0 */
+ au_writel(0x00, 0xb1520004); /* macen1 */
+ au_writel(0x00, 0xb1100100); /* uart0_enable */
+ au_writel(0x00, 0xb1400100); /* uart3_enable */
+ au_writel(0x00, 0xb1900020); /* sys_freqctrl0 */
+ au_writel(0x00, 0xb1900024); /* sys_freqctrl1 */
+ au_writel(0x00, 0xb1900028); /* sys_clksrc */
+ au_writel(0x10, 0xb1900060); /* sys_cpupll */
+ au_writel(0x00, 0xb1900064); /* sys_auxpll */
+ au_writel(0x00, 0xb1900100); /* sys_pininputen */
+ break;
+ case 0x02000000: /* Au1100 */
+ au_writel(0x02, 0xb0000010); /* ac97_enable */
+ au_writel(0x08, 0xb017fffc); /* usbh_enable - early errata */
+ asm("sync");
+ au_writel(0x00, 0xb017fffc); /* usbh_enable */
+ au_writel(0x00, 0xb0200058); /* usbd_enable */
+ au_writel(0x00, 0xb0300040); /* ir_enable */
+ au_writel(0x00, 0xb4004104); /* mac dma */
+ au_writel(0x00, 0xb4004114); /* mac dma */
+ au_writel(0x00, 0xb4004124); /* mac dma */
+ au_writel(0x00, 0xb4004134); /* mac dma */
+ au_writel(0x00, 0xb0520000); /* macen0 */
+ au_writel(0x00, 0xb1000008); /* i2s_enable */
+ au_writel(0x00, 0xb1100100); /* uart0_enable */
+ au_writel(0x00, 0xb1200100); /* uart1_enable */
+ au_writel(0x00, 0xb1400100); /* uart3_enable */
+ au_writel(0x02, 0xb1600100); /* ssi0_enable */
+ au_writel(0x02, 0xb1680100); /* ssi1_enable */
+ au_writel(0x00, 0xb1900020); /* sys_freqctrl0 */
+ au_writel(0x00, 0xb1900024); /* sys_freqctrl1 */
+ au_writel(0x00, 0xb1900028); /* sys_clksrc */
+ au_writel(0x10, 0xb1900060); /* sys_cpupll */
+ au_writel(0x00, 0xb1900064); /* sys_auxpll */
+ au_writel(0x00, 0xb1900100); /* sys_pininputen */
+ break;
+ case 0x03000000: /* Au1550 */
+ au_writel(0x00, 0xb1a00004); /* psc 0 */
+ au_writel(0x00, 0xb1b00004); /* psc 1 */
+ au_writel(0x00, 0xb0a00004); /* psc 2 */
+ au_writel(0x00, 0xb0b00004); /* psc 3 */
+ au_writel(0x00, 0xb017fffc); /* usbh_enable */
+ au_writel(0x00, 0xb0200058); /* usbd_enable */
+ au_writel(0x00, 0xb4004104); /* mac dma */
+ au_writel(0x00, 0xb4004114); /* mac dma */
+ au_writel(0x00, 0xb4004124); /* mac dma */
+ au_writel(0x00, 0xb4004134); /* mac dma */
+ au_writel(0x00, 0xb1520000); /* macen0 */
+ au_writel(0x00, 0xb1520004); /* macen1 */
+ au_writel(0x00, 0xb1100100); /* uart0_enable */
+ au_writel(0x00, 0xb1200100); /* uart1_enable */
+ au_writel(0x00, 0xb1400100); /* uart3_enable */
+ au_writel(0x00, 0xb1900020); /* sys_freqctrl0 */
+ au_writel(0x00, 0xb1900024); /* sys_freqctrl1 */
+ au_writel(0x00, 0xb1900028); /* sys_clksrc */
+ au_writel(0x10, 0xb1900060); /* sys_cpupll */
+ au_writel(0x00, 0xb1900064); /* sys_auxpll */
+ au_writel(0x00, 0xb1900100); /* sys_pininputen */
+ break;
+
+ default:
+ break;
+ }
+
+ set_c0_status(ST0_BEV | ST0_ERL);
+ set_c0_config(CONF_CM_UNCACHED);
+ flush_cache_all();
+ write_c0_wired(0);
+
+ /* Give board a chance to do a hardware reset */
+ board_reset();
+
+ /* Jump to the beggining in case board_reset() is empty */
+ __asm__ __volatile__("jr\t%0"::"r"(0xbfc00000));
+}
+
+void au1000_halt(void)
+{
+#if defined(CONFIG_MIPS_PB1550)
+ /* power off system */
+ printk("\n** Powering off Pb1550\n");
+ au_writew(au_readw(0xAF00001C) | (3<<14), 0xAF00001C);
+ au_sync();
+ while(1); /* should not get here */
+#endif
+ printk(KERN_NOTICE "\n** You can safely turn off the power\n");
+#ifdef CONFIG_MIPS_MIRAGE
+ au_writel((1 << 26) | (1 << 10), GPIO2_OUTPUT);
+#endif
+#ifdef CONFIG_PM
+ au_sleep();
+
+ /* should not get here */
+ printk(KERN_ERR "Unable to put cpu in sleep mode\n");
+ while(1);
+#else
+ while (1)
+ __asm__(".set\tmips3\n\t"
+ "wait\n\t"
+ ".set\tmips0");
+#endif
+}
+
+void au1000_power_off(void)
+{
+ au1000_halt();
+}
diff --git a/arch/mips/au1000/common/setup.c b/arch/mips/au1000/common/setup.c
new file mode 100644
index 00000000000..dbc8b1bda96
--- /dev/null
+++ b/arch/mips/au1000/common/setup.c
@@ -0,0 +1,195 @@
+/*
+ * Copyright 2000 MontaVista Software Inc.
+ * Author: MontaVista Software, Inc.
+ * ppopov@mvista.com or source@mvista.com
+ *
+ * Updates to 2.6, Pete Popov, Embedded Alley Solutions, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#include <linux/config.h>
+#include <linux/init.h>
+#include <linux/sched.h>
+#include <linux/ioport.h>
+#include <linux/mm.h>
+#include <linux/delay.h>
+#include <linux/interrupt.h>
+
+#include <asm/cpu.h>
+#include <asm/bootinfo.h>
+#include <asm/irq.h>
+#include <asm/mipsregs.h>
+#include <asm/reboot.h>
+#include <asm/pgtable.h>
+#include <asm/mach-au1x00/au1000.h>
+#include <asm/time.h>
+
+extern char * __init prom_getcmdline(void);
+extern void __init board_setup(void);
+extern void au1000_restart(char *);
+extern void au1000_halt(void);
+extern void au1000_power_off(void);
+extern struct resource ioport_resource;
+extern struct resource iomem_resource;
+extern void (*board_time_init)(void);
+extern void au1x_time_init(void);
+extern void (*board_timer_setup)(struct irqaction *irq);
+extern void au1x_timer_setup(struct irqaction *irq);
+extern void au1xxx_time_init(void);
+extern void au1xxx_timer_setup(struct irqaction *irq);
+extern void set_cpuspec(void);
+
+static int __init au1x00_setup(void)
+{
+ struct cpu_spec *sp;
+ char *argptr;
+ unsigned long prid, cpupll, bclk = 1;
+
+ set_cpuspec();
+ sp = cur_cpu_spec[0];
+
+ board_setup(); /* board specific setup */
+
+ prid = read_c0_prid();
+ cpupll = (au_readl(0xB1900060) & 0x3F) * 12;
+ printk("(PRId %08lx) @ %ldMHZ\n", prid, cpupll);
+
+ bclk = sp->cpu_bclk;
+ if (bclk)
+ {
+ /* Enable BCLK switching */
+ bclk = au_readl(0xB190003C);
+ au_writel(bclk | 0x60, 0xB190003C);
+ printk("BCLK switching enabled!\n");
+ }
+
+ if (sp->cpu_od) {
+ /* Various early Au1000 Errata corrected by this */
+ set_c0_config(1<<19); /* Set Config[OD] */
+ }
+ else {
+ /* Clear to obtain best system bus performance */
+ clear_c0_config(1<<19); /* Clear Config[OD] */
+ }
+
+ argptr = prom_getcmdline();
+
+#ifdef CONFIG_SERIAL_AU1X00_CONSOLE
+ if ((argptr = strstr(argptr, "console=")) == NULL) {
+ argptr = prom_getcmdline();
+ strcat(argptr, " console=ttyS0,115200");
+ }
+#endif
+
+#ifdef CONFIG_FB_AU1100
+ if ((argptr = strstr(argptr, "video=")) == NULL) {
+ argptr = prom_getcmdline();
+ /* default panel */
+ /*strcat(argptr, " video=au1100fb:panel:Sharp_320x240_16");*/
+#ifdef CONFIG_MIPS_HYDROGEN3
+ strcat(argptr, " video=au1100fb:panel:Hydrogen_3_NEC_panel_320x240,nohwcursor");
+#else
+ strcat(argptr, " video=au1100fb:panel:s10,nohwcursor");
+#endif
+ }
+#endif
+
+#ifdef CONFIG_FB_E1356
+ if ((argptr = strstr(argptr, "video=")) == NULL) {
+ argptr = prom_getcmdline();
+#ifdef CONFIG_MIPS_PB1000
+ strcat(argptr, " video=e1356fb:system:pb1000,mmunalign:1");
+#else
+ strcat(argptr, " video=e1356fb:system:pb1500");
+#endif
+ }
+#endif
+
+#ifdef CONFIG_FB_XPERT98
+ if ((argptr = strstr(argptr, "video=")) == NULL) {
+ argptr = prom_getcmdline();
+ strcat(argptr, " video=atyfb:1024x768-8@70");
+ }
+#endif
+
+#if defined(CONFIG_SOUND_AU1X00) && !defined(CONFIG_SOC_AU1000)
+ /* au1000 does not support vra, au1500 and au1100 do */
+ strcat(argptr, " au1000_audio=vra");
+ argptr = prom_getcmdline();
+#endif
+ _machine_restart = au1000_restart;
+ _machine_halt = au1000_halt;
+ _machine_power_off = au1000_power_off;
+ board_time_init = au1xxx_time_init;
+ board_timer_setup = au1xxx_timer_setup;
+
+ /* IO/MEM resources. */
+ set_io_port_base(0);
+ ioport_resource.start = IOPORT_RESOURCE_START;
+ ioport_resource.end = IOPORT_RESOURCE_END;
+ iomem_resource.start = IOMEM_RESOURCE_START;
+ iomem_resource.end = IOMEM_RESOURCE_END;
+
+ while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_E0S);
+ au_writel(SYS_CNTRL_E0 | SYS_CNTRL_EN0, SYS_COUNTER_CNTRL);
+ au_sync();
+ while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T0S);
+ au_writel(0, SYS_TOYTRIM);
+
+ return 0;
+}
+
+early_initcall(au1x00_setup);
+
+#if defined(CONFIG_64BIT_PHYS_ADDR)
+/* This routine should be valid for all Au1x based boards */
+phys_t fixup_bigphys_addr(phys_t phys_addr, phys_t size)
+{
+ u32 start, end;
+
+ /* Don't fixup 36 bit addresses */
+ if ((phys_addr >> 32) != 0) return phys_addr;
+
+#ifdef CONFIG_PCI
+ start = (u32)Au1500_PCI_MEM_START;
+ end = (u32)Au1500_PCI_MEM_END;
+ /* check for pci memory window */
+ if ((phys_addr >= start) && ((phys_addr + size) < end)) {
+ return (phys_t)((phys_addr - start) + Au1500_PCI_MEM_START);
+ }
+#endif
+
+ /* All Au1x SOCs have a pcmcia controller */
+ /* We setup our 32 bit pseudo addresses to be equal to the
+ * 36 bit addr >> 4, to make it easier to check the address
+ * and fix it.
+ * The Au1x socket 0 phys attribute address is 0xF 4000 0000.
+ * The pseudo address we use is 0xF400 0000. Any address over
+ * 0xF400 0000 is a pcmcia pseudo address.
+ */
+ if ((phys_addr >= 0xF4000000) && (phys_addr < 0xFFFFFFFF)) {
+ return (phys_t)(phys_addr << 4);
+ }
+
+ /* default nop */
+ return phys_addr;
+}
+#endif
diff --git a/arch/mips/au1000/common/sleeper.S b/arch/mips/au1000/common/sleeper.S
new file mode 100644
index 00000000000..44dac3b0df3
--- /dev/null
+++ b/arch/mips/au1000/common/sleeper.S
@@ -0,0 +1,149 @@
+/*
+ * Copyright 2002 Embedded Edge, LLC
+ * Author: dan@embeddededge.com
+ *
+ * Sleep helper for Au1xxx sleep mode.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+#include <asm/asm.h>
+#include <asm/mipsregs.h>
+#include <asm/addrspace.h>
+#include <asm/regdef.h>
+#include <asm/stackframe.h>
+
+ .text
+ .set macro
+ .set noat
+ .align 5
+
+/* Save all of the processor general registers and go to sleep.
+ * A wakeup condition will get us back here to restore the registers.
+ */
+LEAF(save_and_sleep)
+
+ subu sp, PT_SIZE
+ sw $1, PT_R1(sp)
+ sw $2, PT_R2(sp)
+ sw $3, PT_R3(sp)
+ sw $4, PT_R4(sp)
+ sw $5, PT_R5(sp)
+ sw $6, PT_R6(sp)
+ sw $7, PT_R7(sp)
+ sw $8, PT_R8(sp)
+ sw $9, PT_R9(sp)
+ sw $10, PT_R10(sp)
+ sw $11, PT_R11(sp)
+ sw $12, PT_R12(sp)
+ sw $13, PT_R13(sp)
+ sw $14, PT_R14(sp)
+ sw $15, PT_R15(sp)
+ sw $16, PT_R16(sp)
+ sw $17, PT_R17(sp)
+ sw $18, PT_R18(sp)
+ sw $19, PT_R19(sp)
+ sw $20, PT_R20(sp)
+ sw $21, PT_R21(sp)
+ sw $22, PT_R22(sp)
+ sw $23, PT_R23(sp)
+ sw $24, PT_R24(sp)
+ sw $25, PT_R25(sp)
+ sw $26, PT_R26(sp)
+ sw $27, PT_R27(sp)
+ sw $28, PT_R28(sp)
+ sw $29, PT_R29(sp)
+ sw $30, PT_R30(sp)
+ sw $31, PT_R31(sp)
+ mfc0 k0, CP0_STATUS
+ sw k0, 0x20(sp)
+ mfc0 k0, CP0_CONTEXT
+ sw k0, 0x1c(sp)
+ mfc0 k0, CP0_PAGEMASK
+ sw k0, 0x18(sp)
+ mfc0 k0, CP0_CONFIG
+ sw k0, 0x14(sp)
+
+ /* Now set up the scratch registers so the boot rom will
+ * return to this point upon wakeup.
+ */
+ la k0, 1f
+ lui k1, 0xb190
+ ori k1, 0x18
+ sw sp, 0(k1)
+ ori k1, 0x1c
+ sw k0, 0(k1)
+
+/* Put SDRAM into self refresh. Preload instructions into cache,
+ * issue a precharge, then auto refresh, then sleep commands to it.
+ */
+ la t0, sdsleep
+ .set mips3
+ cache 0x14, 0(t0)
+ cache 0x14, 32(t0)
+ cache 0x14, 64(t0)
+ cache 0x14, 96(t0)
+ .set mips0
+
+sdsleep:
+ lui k0, 0xb400
+ sw zero, 0x001c(k0) /* Precharge */
+ sw zero, 0x0020(k0) /* Auto refresh */
+ sw zero, 0x0030(k0) /* SDRAM sleep */
+ sync
+
+ lui k1, 0xb190
+ sw zero, 0x0078(k1) /* get ready to sleep */
+ sync
+ sw zero, 0x007c(k1) /* Put processor to sleep */
+ sync
+
+ /* This is where we return upon wakeup.
+ * Reload all of the registers and return.
+ */
+1: nop
+ lw k0, 0x20(sp)
+ mtc0 k0, CP0_STATUS
+ lw k0, 0x1c(sp)
+ mtc0 k0, CP0_CONTEXT
+ lw k0, 0x18(sp)
+ mtc0 k0, CP0_PAGEMASK
+ lw k0, 0x14(sp)
+ mtc0 k0, CP0_CONFIG
+ lw $1, PT_R1(sp)
+ lw $2, PT_R2(sp)
+ lw $3, PT_R3(sp)
+ lw $4, PT_R4(sp)
+ lw $5, PT_R5(sp)
+ lw $6, PT_R6(sp)
+ lw $7, PT_R7(sp)
+ lw $8, PT_R8(sp)
+ lw $9, PT_R9(sp)
+ lw $10, PT_R10(sp)
+ lw $11, PT_R11(sp)
+ lw $12, PT_R12(sp)
+ lw $13, PT_R13(sp)
+ lw $14, PT_R14(sp)
+ lw $15, PT_R15(sp)
+ lw $16, PT_R16(sp)
+ lw $17, PT_R17(sp)
+ lw $18, PT_R18(sp)
+ lw $19, PT_R19(sp)
+ lw $20, PT_R20(sp)
+ lw $21, PT_R21(sp)
+ lw $22, PT_R22(sp)
+ lw $23, PT_R23(sp)
+ lw $24, PT_R24(sp)
+ lw $25, PT_R25(sp)
+ lw $26, PT_R26(sp)
+ lw $27, PT_R27(sp)
+ lw $28, PT_R28(sp)
+ lw $29, PT_R29(sp)
+ lw $30, PT_R30(sp)
+ lw $31, PT_R31(sp)
+ addiu sp, PT_SIZE
+
+ jr ra
+END(save_and_sleep)
diff --git a/arch/mips/au1000/common/time.c b/arch/mips/au1000/common/time.c
new file mode 100644
index 00000000000..fe418f1620c
--- /dev/null
+++ b/arch/mips/au1000/common/time.c
@@ -0,0 +1,469 @@
+/*
+ *
+ * Copyright (C) 2001 MontaVista Software, ppopov@mvista.com
+ * Copied and modified Carsten Langgaard's time.c
+ *
+ * Carsten Langgaard, carstenl@mips.com
+ * Copyright (C) 1999,2000 MIPS Technologies, Inc. All rights reserved.
+ *
+ * ########################################################################
+ *
+ * This program is free software; you can distribute it and/or modify it
+ * under the terms of the GNU General Public License (Version 2) as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
+ * for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 59 Temple Place - Suite 330, Boston MA 02111-1307, USA.
+ *
+ * ########################################################################
+ *
+ * Setting up the clock on the MIPS boards.
+ *
+ * Update. Always configure the kernel with CONFIG_NEW_TIME_C. This
+ * will use the user interface gettimeofday() functions from the
+ * arch/mips/kernel/time.c, and we provide the clock interrupt processing
+ * and the timer offset compute functions. If CONFIG_PM is selected,
+ * we also ensure the 32KHz timer is available. -- Dan
+ */
+
+#include <linux/types.h>
+#include <linux/config.h>
+#include <linux/init.h>
+#include <linux/kernel_stat.h>
+#include <linux/sched.h>
+#include <linux/spinlock.h>
+#include <linux/hardirq.h>
+
+#include <asm/compiler.h>
+#include <asm/mipsregs.h>
+#include <asm/ptrace.h>
+#include <asm/time.h>
+#include <asm/div64.h>
+#include <asm/mach-au1x00/au1000.h>
+
+#include <linux/mc146818rtc.h>
+#include <linux/timex.h>
+
+extern void startup_match20_interrupt(void);
+extern void do_softirq(void);
+extern volatile unsigned long wall_jiffies;
+unsigned long missed_heart_beats = 0;
+
+static unsigned long r4k_offset; /* Amount to increment compare reg each time */
+static unsigned long r4k_cur; /* What counter should be at next timer irq */
+int no_au1xxx_32khz;
+void (*au1k_wait_ptr)(void);
+
+/* Cycle counter value at the previous timer interrupt.. */
+static unsigned int timerhi = 0, timerlo = 0;
+
+#ifdef CONFIG_PM
+#define MATCH20_INC 328
+extern void startup_match20_interrupt(void);
+static unsigned long last_pc0, last_match20;
+#endif
+
+static DEFINE_SPINLOCK(time_lock);
+
+static inline void ack_r4ktimer(unsigned long newval)
+{
+ write_c0_compare(newval);
+}
+
+/*
+ * There are a lot of conceptually broken versions of the MIPS timer interrupt
+ * handler floating around. This one is rather different, but the algorithm
+ * is provably more robust.
+ */
+unsigned long wtimer;
+void mips_timer_interrupt(struct pt_regs *regs)
+{
+ int irq = 63;
+ unsigned long count;
+
+ irq_enter();
+ kstat_this_cpu.irqs[irq]++;
+
+ if (r4k_offset == 0)
+ goto null;
+
+ do {
+ count = read_c0_count();
+ timerhi += (count < timerlo); /* Wrap around */
+ timerlo = count;
+
+ kstat_this_cpu.irqs[irq]++;
+ do_timer(regs);
+#ifndef CONFIG_SMP
+ update_process_times(user_mode(regs));
+#endif
+ r4k_cur += r4k_offset;
+ ack_r4ktimer(r4k_cur);
+
+ } while (((unsigned long)read_c0_count()
+ - r4k_cur) < 0x7fffffff);
+
+ irq_exit();
+ return;
+
+null:
+ ack_r4ktimer(0);
+}
+
+#ifdef CONFIG_PM
+void counter0_irq(int irq, void *dev_id, struct pt_regs *regs)
+{
+ unsigned long pc0;
+ int time_elapsed;
+ static int jiffie_drift = 0;
+
+ kstat.irqs[0][irq]++;
+ if (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20) {
+ /* should never happen! */
+ printk(KERN_WARNING "counter 0 w status eror\n");
+ return;
+ }
+
+ pc0 = au_readl(SYS_TOYREAD);
+ if (pc0 < last_match20) {
+ /* counter overflowed */
+ time_elapsed = (0xffffffff - last_match20) + pc0;
+ }
+ else {
+ time_elapsed = pc0 - last_match20;
+ }
+
+ while (time_elapsed > 0) {
+ do_timer(regs);
+#ifndef CONFIG_SMP
+ update_process_times(user_mode(regs));
+#endif
+ time_elapsed -= MATCH20_INC;
+ last_match20 += MATCH20_INC;
+ jiffie_drift++;
+ }
+
+ last_pc0 = pc0;
+ au_writel(last_match20 + MATCH20_INC, SYS_TOYMATCH2);
+ au_sync();
+
+ /* our counter ticks at 10.009765625 ms/tick, we we're running
+ * almost 10uS too slow per tick.
+ */
+
+ if (jiffie_drift >= 999) {
+ jiffie_drift -= 999;
+ do_timer(regs); /* increment jiffies by one */
+#ifndef CONFIG_SMP
+ update_process_times(user_mode(regs));
+#endif
+ }
+}
+
+/* When we wakeup from sleep, we have to "catch up" on all of the
+ * timer ticks we have missed.
+ */
+void
+wakeup_counter0_adjust(void)
+{
+ unsigned long pc0;
+ int time_elapsed;
+
+ pc0 = au_readl(SYS_TOYREAD);
+ if (pc0 < last_match20) {
+ /* counter overflowed */
+ time_elapsed = (0xffffffff - last_match20) + pc0;
+ }
+ else {
+ time_elapsed = pc0 - last_match20;
+ }
+
+ while (time_elapsed > 0) {
+ time_elapsed -= MATCH20_INC;
+ last_match20 += MATCH20_INC;
+ }
+
+ last_pc0 = pc0;
+ au_writel(last_match20 + MATCH20_INC, SYS_TOYMATCH2);
+ au_sync();
+
+}
+
+/* This is just for debugging to set the timer for a sleep delay.
+*/
+void
+wakeup_counter0_set(int ticks)
+{
+ unsigned long pc0;
+
+ pc0 = au_readl(SYS_TOYREAD);
+ last_pc0 = pc0;
+ au_writel(last_match20 + (MATCH20_INC * ticks), SYS_TOYMATCH2);
+ au_sync();
+}
+#endif
+
+/* I haven't found anyone that doesn't use a 12 MHz source clock,
+ * but just in case.....
+ */
+#ifdef CONFIG_AU1000_SRC_CLK
+#define AU1000_SRC_CLK CONFIG_AU1000_SRC_CLK
+#else
+#define AU1000_SRC_CLK 12000000
+#endif
+
+/*
+ * We read the real processor speed from the PLL. This is important
+ * because it is more accurate than computing it from the 32KHz
+ * counter, if it exists. If we don't have an accurate processor
+ * speed, all of the peripherals that derive their clocks based on
+ * this advertised speed will introduce error and sometimes not work
+ * properly. This function is futher convoluted to still allow configurations
+ * to do that in case they have really, really old silicon with a
+ * write-only PLL register, that we need the 32KHz when power management
+ * "wait" is enabled, and we need to detect if the 32KHz isn't present
+ * but requested......got it? :-) -- Dan
+ */
+unsigned long cal_r4koff(void)
+{
+ unsigned long count;
+ unsigned long cpu_speed;
+ unsigned long flags;
+ unsigned long counter;
+
+ spin_lock_irqsave(&time_lock, flags);
+
+ /* Power management cares if we don't have a 32KHz counter.
+ */
+ no_au1xxx_32khz = 0;
+ counter = au_readl(SYS_COUNTER_CNTRL);
+ if (counter & SYS_CNTRL_E0) {
+ int trim_divide = 16;
+
+ au_writel(counter | SYS_CNTRL_EN1, SYS_COUNTER_CNTRL);
+
+ while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T1S);
+ /* RTC now ticks at 32.768/16 kHz */
+ au_writel(trim_divide-1, SYS_RTCTRIM);
+ while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_T1S);
+
+ while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S);
+ au_writel (0, SYS_TOYWRITE);
+ while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C1S);
+
+#if defined(CONFIG_AU1000_USE32K)
+ {
+ unsigned long start, end;
+
+ start = au_readl(SYS_RTCREAD);
+ start += 2;
+ /* wait for the beginning of a new tick
+ */
+ while (au_readl(SYS_RTCREAD) < start);
+
+ /* Start r4k counter.
+ */
+ write_c0_count(0);
+
+ /* Wait 0.5 seconds.
+ */
+ end = start + (32768 / trim_divide)/2;
+
+ while (end > au_readl(SYS_RTCREAD));
+
+ count = read_c0_count();
+ cpu_speed = count * 2;
+ }
+#else
+ cpu_speed = (au_readl(SYS_CPUPLL) & 0x0000003f) *
+ AU1000_SRC_CLK;
+ count = cpu_speed / 2;
+#endif
+ }
+ else {
+ /* The 32KHz oscillator isn't running, so assume there
+ * isn't one and grab the processor speed from the PLL.
+ * NOTE: some old silicon doesn't allow reading the PLL.
+ */
+ cpu_speed = (au_readl(SYS_CPUPLL) & 0x0000003f) * AU1000_SRC_CLK;
+ count = cpu_speed / 2;
+ no_au1xxx_32khz = 1;
+ }
+ mips_hpt_frequency = count;
+ // Equation: Baudrate = CPU / (SD * 2 * CLKDIV * 16)
+ set_au1x00_uart_baud_base(cpu_speed / (2 * ((int)(au_readl(SYS_POWERCTRL)&0x03) + 2) * 16));
+ spin_unlock_irqrestore(&time_lock, flags);
+ return (cpu_speed / HZ);
+}
+
+/* This is for machines which generate the exact clock. */
+#define USECS_PER_JIFFY (1000000/HZ)
+#define USECS_PER_JIFFY_FRAC (0x100000000LL*1000000/HZ&0xffffffff)
+
+static unsigned long
+div64_32(unsigned long v1, unsigned long v2, unsigned long v3)
+{
+ unsigned long r0;
+ do_div64_32(r0, v1, v2, v3);
+ return r0;
+}
+
+static unsigned long do_fast_cp0_gettimeoffset(void)
+{
+ u32 count;
+ unsigned long res, tmp;
+ unsigned long r0;
+
+ /* Last jiffy when do_fast_gettimeoffset() was called. */
+ static unsigned long last_jiffies=0;
+ unsigned long quotient;
+
+ /*
+ * Cached "1/(clocks per usec)*2^32" value.
+ * It has to be recalculated once each jiffy.
+ */
+ static unsigned long cached_quotient=0;
+
+ tmp = jiffies;
+
+ quotient = cached_quotient;
+
+ if (tmp && last_jiffies != tmp) {
+ last_jiffies = tmp;
+ if (last_jiffies != 0) {
+ r0 = div64_32(timerhi, timerlo, tmp);
+ quotient = div64_32(USECS_PER_JIFFY, USECS_PER_JIFFY_FRAC, r0);
+ cached_quotient = quotient;
+ }
+ }
+
+ /* Get last timer tick in absolute kernel time */
+ count = read_c0_count();
+
+ /* .. relative to previous jiffy (32 bits is enough) */
+ count -= timerlo;
+
+ __asm__("multu\t%1,%2\n\t"
+ "mfhi\t%0"
+ : "=r" (res)
+ : "r" (count), "r" (quotient)
+ : "hi", "lo", GCC_REG_ACCUM);
+
+ /*
+ * Due to possible jiffies inconsistencies, we need to check
+ * the result so that we'll get a timer that is monotonic.
+ */
+ if (res >= USECS_PER_JIFFY)
+ res = USECS_PER_JIFFY-1;
+
+ return res;
+}
+
+#ifdef CONFIG_PM
+static unsigned long do_fast_pm_gettimeoffset(void)
+{
+ unsigned long pc0;
+ unsigned long offset;
+
+ pc0 = au_readl(SYS_TOYREAD);
+ au_sync();
+ offset = pc0 - last_pc0;
+ if (offset > 2*MATCH20_INC) {
+ printk("huge offset %x, last_pc0 %x last_match20 %x pc0 %x\n",
+ (unsigned)offset, (unsigned)last_pc0,
+ (unsigned)last_match20, (unsigned)pc0);
+ }
+ offset = (unsigned long)((offset * 305) / 10);
+ return offset;
+}
+#endif
+
+void au1xxx_timer_setup(struct irqaction *irq)
+{
+ unsigned int est_freq;
+ extern unsigned long (*do_gettimeoffset)(void);
+ extern void au1k_wait(void);
+
+ printk("calculating r4koff... ");
+ r4k_offset = cal_r4koff();
+ printk("%08lx(%d)\n", r4k_offset, (int) r4k_offset);
+
+ //est_freq = 2*r4k_offset*HZ;
+ est_freq = r4k_offset*HZ;
+ est_freq += 5000; /* round */
+ est_freq -= est_freq%10000;
+ printk("CPU frequency %d.%02d MHz\n", est_freq/1000000,
+ (est_freq%1000000)*100/1000000);
+ set_au1x00_speed(est_freq);
+ set_au1x00_lcd_clock(); // program the LCD clock
+
+ r4k_cur = (read_c0_count() + r4k_offset);
+ write_c0_compare(r4k_cur);
+
+#ifdef CONFIG_PM
+ /*
+ * setup counter 0, since it keeps ticking after a
+ * 'wait' instruction has been executed. The CP0 timer and
+ * counter 1 do NOT continue running after 'wait'
+ *
+ * It's too early to call request_irq() here, so we handle
+ * counter 0 interrupt as a special irq and it doesn't show
+ * up under /proc/interrupts.
+ *
+ * Check to ensure we really have a 32KHz oscillator before
+ * we do this.
+ */
+ if (no_au1xxx_32khz) {
+ unsigned int c0_status;
+
+ printk("WARNING: no 32KHz clock found.\n");
+ do_gettimeoffset = do_fast_cp0_gettimeoffset;
+
+ /* Ensure we get CPO_COUNTER interrupts.
+ */
+ c0_status = read_c0_status();
+ c0_status |= IE_IRQ5;
+ write_c0_status(c0_status);
+ }
+ else {
+ while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C0S);
+ au_writel(0, SYS_TOYWRITE);
+ while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_C0S);
+
+ au_writel(au_readl(SYS_WAKEMSK) | (1<<8), SYS_WAKEMSK);
+ au_writel(~0, SYS_WAKESRC);
+ au_sync();
+ while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20);
+
+ /* setup match20 to interrupt once every 10ms */
+ last_pc0 = last_match20 = au_readl(SYS_TOYREAD);
+ au_writel(last_match20 + MATCH20_INC, SYS_TOYMATCH2);
+ au_sync();
+ while (au_readl(SYS_COUNTER_CNTRL) & SYS_CNTRL_M20);
+ startup_match20_interrupt();
+
+ do_gettimeoffset = do_fast_pm_gettimeoffset;
+
+ /* We can use the real 'wait' instruction.
+ */
+ au1k_wait_ptr = au1k_wait;
+ }
+
+#else
+ /* We have to do this here instead of in timer_init because
+ * the generic code in arch/mips/kernel/time.c will write
+ * over our function pointer.
+ */
+ do_gettimeoffset = do_fast_cp0_gettimeoffset;
+#endif
+}
+
+void __init au1xxx_time_init(void)
+{
+}
diff --git a/arch/mips/au1000/common/usbdev.c b/arch/mips/au1000/common/usbdev.c
new file mode 100644
index 00000000000..447a9a4612a
--- /dev/null
+++ b/arch/mips/au1000/common/usbdev.c
@@ -0,0 +1,1557 @@
+/*
+ * BRIEF MODULE DESCRIPTION
+ * Au1000 USB Device-Side (device layer)
+ *
+ * Copyright 2001-2002 MontaVista Software Inc.
+ * Author: MontaVista Software, Inc.
+ * stevel@mvista.com or source@mvista.com
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ *
+ * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
+ * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN
+ * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
+ * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF
+ * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
+ * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, write to the Free Software Foundation, Inc.,
+ * 675 Mass Ave, Cambridge, MA 02139, USA.
+ */
+#include <linux/kernel.h>
+#include <linux/ioport.h>
+#include <linux/sched.h>
+#include <linux/signal.h>
+#include <linux/errno.h>
+#include <linux/poll.h>
+#include <linux/init.h>
+#include <linux/slab.h>
+#include <linux/fcntl.h>
+#include <linux/module.h>
+#include <linux/spinlock.h>
+#include <linux/list.h>
+#include <linux/smp_lock.h>
+#define DEBUG
+#include <linux/usb.h>
+
+#include <asm/io.h>
+#include <asm/uaccess.h>
+#include <asm/irq.h>
+#include <asm/mipsregs.h>
+#include <asm/au1000.h>
+#include <asm/au1000_dma.h>
+#include <asm/au1000_usbdev.h>
+
+#ifdef DEBUG
+#undef VDEBUG
+#ifdef VDEBUG
+#define vdbg(fmt, arg...) printk(KERN_DEBUG __FILE__ ": " fmt "\n" , ## arg)
+#else
+#define vdbg(fmt, arg...) do {} while (0)
+#endif
+#else
+#define vdbg(fmt, arg...) do {} while (0)
+#endif
+
+#define ALLOC_FLAGS (in_interrupt () ? GFP_ATOMIC : GFP_KERNEL)
+
+#define EP_FIFO_DEPTH 8
+
+typedef enum {
+ SETUP_STAGE = 0,
+ DATA_STAGE,
+ STATUS_STAGE
+} ep0_stage_t;
+
+typedef struct {
+ int read_fifo;
+ int write_fifo;
+ int ctrl_stat;
+ int read_fifo_status;
+ int write_fifo_status;
+} endpoint_reg_t;
+
+typedef struct {
+ usbdev_pkt_t *head;
+ usbdev_pkt_t *tail;
+ int count;
+} pkt_list_t;
+
+typedef struct {
+ int active;
+ struct usb_endpoint_descriptor *desc;
+ endpoint_reg_t *reg;
+ /* Only one of these are used, unless this is the control ep */
+ pkt_list_t inlist;
+ pkt_list_t outlist;
+ unsigned int indma, outdma; /* DMA channel numbers for IN, OUT */
+ /* following are extracted from endpoint descriptor for easy access */
+ int max_pkt_size;
+ int type;
+ int direction;
+ /* WE assign endpoint addresses! */
+ int address;
+ spinlock_t lock;
+} endpoint_t;
+
+
+static struct usb_dev {
+ endpoint_t ep[6];
+ ep0_stage_t ep0_stage;
+
+ struct usb_device_descriptor * dev_desc;
+ struct usb_interface_descriptor* if_desc;
+ struct usb_config_descriptor * conf_desc;
+ u8 * full_conf_desc;
+ struct usb_string_descriptor * str_desc[6];
+
+ /* callback to function layer */
+ void (*func_cb)(usbdev_cb_type_t type, unsigned long arg,
+ void *cb_data);
+ void* cb_data;
+
+ usbdev_state_t state; // device state
+ int suspended; // suspended flag
+ int address; // device address
+ int interface;
+ int num_ep;
+ u8 alternate_setting;
+ u8 configuration; // configuration value
+ int remote_wakeup_en;
+} usbdev;
+
+
+static endpoint_reg_t ep_reg[] = {
+ // FIFO's 0 and 1 are EP0 default control
+ {USBD_EP0RD, USBD_EP0WR, USBD_EP0CS, USBD_EP0RDSTAT, USBD_EP0WRSTAT },
+ {0},
+ // FIFO 2 is EP2, IN
+ { -1, USBD_EP2WR, USBD_EP2CS, -1, USBD_EP2WRSTAT },
+ // FIFO 3 is EP3, IN
+ { -1, USBD_EP3WR, USBD_EP3CS, -1, USBD_EP3WRSTAT },
+ // FIFO 4 is EP4, OUT
+ {USBD_EP4RD, -1, USBD_EP4CS, USBD_EP4RDSTAT, -1 },
+ // FIFO 5 is EP5, OUT
+ {USBD_EP5RD, -1, USBD_EP5CS, USBD_EP5RDSTAT, -1 }
+};
+
+static struct {
+ unsigned int id;
+ const char *str;
+} ep_dma_id[] = {
+ { DMA_ID_USBDEV_EP0_TX, "USBDev EP0 IN" },
+ { DMA_ID_USBDEV_EP0_RX, "USBDev EP0 OUT" },
+ { DMA_ID_USBDEV_EP2_TX, "USBDev EP2 IN" },
+ { DMA_ID_USBDEV_EP3_TX, "USBDev EP3 IN" },
+ { DMA_ID_USBDEV_EP4_RX, "USBDev EP4 OUT" },
+ { DMA_ID_USBDEV_EP5_RX, "USBDev EP5 OUT" }
+};
+
+#define DIR_OUT 0
+#define DIR_IN (1<<3)
+
+#define CONTROL_EP USB_ENDPOINT_XFER_CONTROL
+#define BULK_EP USB_ENDPOINT_XFER_BULK
+
+static inline endpoint_t *
+epaddr_to_ep(struct usb_dev* dev, int ep_addr)
+{
+ if (ep_addr >= 0 && ep_addr < 2)
+ return &dev->ep[0];
+ if (ep_addr < 6)
+ return &dev->ep[ep_addr];
+ return NULL;
+}
+
+static const char* std_req_name[] = {
+ "GET_STATUS",
+ "CLEAR_FEATURE",
+ "RESERVED",
+ "SET_FEATURE",
+ "RESERVED",
+ "SET_ADDRESS",
+ "GET_DESCRIPTOR",
+ "SET_DESCRIPTOR",
+ "GET_CONFIGURATION",
+ "SET_CONFIGURATION",
+ "GET_INTERFACE",
+ "SET_INTERFACE",
+ "SYNCH_FRAME"
+};
+
+static inline const char*
+get_std_req_name(int req)
+{
+ return (req >= 0 && req <= 12) ? std_req_name[req] : "UNKNOWN";
+}
+
+#if 0
+static void
+dump_setup(struct usb_ctrlrequest* s)
+{
+ dbg("%s: requesttype=%d", __FUNCTION__, s->requesttype);
+ dbg("%s: request=%d %s", __FUNCTION__, s->request,
+ get_std_req_name(s->request));
+ dbg("%s: value=0x%04x", __FUNCTION__, s->wValue);
+ dbg("%s: index=%d", __FUNCTION__, s->index);
+ dbg("%s: length=%d", __FUNCTION__, s->length);
+}
+#endif
+
+static inline usbdev_pkt_t *
+alloc_packet(endpoint_t * ep, int data_size, void* data)
+{
+ usbdev_pkt_t* pkt = kmalloc(sizeof(usbdev_pkt_t) + data_size,
+ ALLOC_FLAGS);
+ if (!pkt)
+ return NULL;
+ pkt->ep_addr = ep->address;
+ pkt->size = data_size;
+ pkt->status = 0;
+ pkt->next = NULL;
+ if (data)
+ memcpy(pkt->payload, data, data_size);
+
+ return pkt;
+}
+
+
+/*
+ * Link a packet to the tail of the enpoint's packet list.
+ * EP spinlock must be held when calling.
+ */
+static void
+link_tail(endpoint_t * ep, pkt_list_t * list, usbdev_pkt_t * pkt)
+{
+ if (!list->tail) {
+ list->head = list->tail = pkt;
+ list->count = 1;
+ } else {
+ list->tail->next = pkt;
+ list->tail = pkt;
+ list->count++;
+ }
+}
+
+/*
+ * Unlink and return a packet from the head of the given packet
+ * list. It is the responsibility of the caller to free the packet.
+ * EP spinlock must be held when calling.
+ */
+static usbdev_pkt_t *
+unlink_head(pkt_list_t * list)
+{
+ usbdev_pkt_t *pkt;
+
+ pkt = list->head;
+ if (!pkt || !list->count) {
+ return NULL;
+ }
+
+ list->head = pkt->next;
+ if (!list->head) {
+ list->head = list->tail = NULL;
+ list->count = 0;
+ } else
+ list->count--;
+
+ return pkt;
+}
+
+/*
+ * Create and attach a new packet to the tail of the enpoint's
+ * packet list. EP spinlock must be held when calling.
+ */
+static usbdev_pkt_t *
+add_packet(endpoint_t * ep, pkt_list_t * list, int size)
+{
+ usbdev_pkt_t *pkt = alloc_packet(ep, size, NULL);
+ if (!pkt)
+ return NULL;
+
+ link_tail(ep, list, pkt);
+ return pkt;
+}
+
+
+/*
+ * Unlink and free a packet from the head of the enpoint's
+ * packet list. EP spinlock must be held when calling.
+ */
+static inline void
+free_packet(pkt_list_t * list)
+{
+ kfree(unlink_head(list));
+}
+
+/* EP spinlock must be held when calling. */
+static inline void
+flush_pkt_list(pkt_list_t * list)
+{
+ while (list->count)
+ free_packet(list);
+}
+
+/* EP spinlock must be held when calling */
+static inline void
+flush_write_fifo(endpoint_t * ep)
+{
+ if (ep->reg->write_fifo_status >= 0) {
+ au_writel(USBDEV_FSTAT_FLUSH | USBDEV_FSTAT_UF |
+ USBDEV_FSTAT_OF,
+ ep->reg->write_fifo_status);
+ //udelay(100);
+ //au_writel(USBDEV_FSTAT_UF | USBDEV_FSTAT_OF,
+ // ep->reg->write_fifo_status);
+ }
+}
+
+/* EP spinlock must be held when calling */
+static inline void
+flush_read_fifo(endpoint_t * ep)
+{
+ if (ep->reg->read_fifo_status >= 0) {
+ au_writel(USBDEV_FSTAT_FLUSH | USBDEV_FSTAT_UF |
+ USBDEV_FSTAT_OF,
+ ep->reg->read_fifo_status);
+ //udelay(100);
+ //au_writel(USBDEV_FSTAT_UF | USBDEV_FSTAT_OF,
+ // ep->reg->read_fifo_status);
+ }
+}
+
+
+/* EP spinlock must be held when calling. */
+static void
+endpoint_flush(endpoint_t * ep)
+{
+ // First, flush all packets
+ flush_pkt_list(&ep->inlist);
+ flush_pkt_list(&ep->outlist);
+
+ // Now flush the endpoint's h/w FIFO(s)
+ flush_write_fifo(ep);
+ flush_read_fifo(ep);
+}
+
+/* EP spinlock must be held when calling. */
+static void
+endpoint_stall(endpoint_t * ep)
+{
+ u32 cs;
+
+ warn(__FUNCTION__);
+
+ cs = au_readl(ep->reg->ctrl_stat) | USBDEV_CS_STALL;
+ au_writel(cs, ep->reg->ctrl_stat);
+}
+
+/* EP spinlock must be held when calling. */
+static void
+endpoint_unstall(endpoint_t * ep)
+{
+ u32 cs;
+
+ warn(__FUNCTION__);
+
+ cs = au_readl(ep->reg->ctrl_stat) & ~USBDEV_CS_STALL;
+ au_writel(cs, ep->reg->ctrl_stat);
+}
+
+static void
+endpoint_reset_datatoggle(endpoint_t * ep)
+{
+ // FIXME: is this possible?
+}
+
+
+/* EP spinlock must be held when calling. */
+static int
+endpoint_fifo_read(endpoint_t * ep)
+{
+ int read_count = 0;
+ u8 *bufptr;
+ usbdev_pkt_t *pkt = ep->outlist.tail;
+
+ if (!pkt)
+ return -EINVAL;
+
+ bufptr = &pkt->payload[pkt->size];
+ while (au_readl(ep->reg->read_fifo_status) & USBDEV_FSTAT_FCNT_MASK) {
+ *bufptr++ = au_readl(ep->reg->read_fifo) & 0xff;
+ read_count++;
+ pkt->size++;
+ }
+
+ return read_count;
+}
+
+#if 0
+/* EP spinlock must be held when calling. */
+static int
+endpoint_fifo_write(endpoint_t * ep, int index)
+{
+ int write_count = 0;
+ u8 *bufptr;
+ usbdev_pkt_t *pkt = ep->inlist.head;
+
+ if (!pkt)
+ return -EINVAL;
+
+ bufptr = &pkt->payload[index];
+ while ((au_readl(ep->reg->write_fifo_status) &
+ USBDEV_FSTAT_FCNT_MASK) < EP_FIFO_DEPTH) {
+ if (bufptr < pkt->payload + pkt->size) {
+ au_writel(*bufptr++, ep->reg->write_fifo);
+ write_count++;
+ } else {
+ break;
+ }
+ }
+
+ return write_count;
+}
+#endif
+
+/*
+ * This routine is called to restart transmission of a packet.
+ * The endpoint's TSIZE must be set to the new packet's size,
+ * and DMA to the write FIFO needs to be restarted.
+ * EP spinlock must be held when calling.
+ */
+static void
+kickstart_send_packet(endpoint_t * ep)
+{
+ u32 cs;
+ usbdev_pkt_t *pkt = ep->inlist.head;
+
+ vdbg("%s: ep%d, pkt=%p", __FUNCTION__, ep->address, pkt);
+
+ if (!pkt) {
+ err("%s: head=NULL! list->count=%d", __FUNCTION__,
+ ep->inlist.count);
+ return;
+ }
+
+ dma_cache_wback_inv((unsigned long)pkt->payload, pkt->size);
+
+ /*
+ * make sure FIFO is empty
+ */
+ flush_write_fifo(ep);
+
+ cs = au_readl(ep->reg->ctrl_stat) & USBDEV_CS_STALL;
+ cs |= (pkt->size << USBDEV_CS_TSIZE_BIT);
+ au_writel(cs, ep->reg->ctrl_stat);
+
+ if (get_dma_active_buffer(ep->indma) == 1) {
+ set_dma_count1(ep->indma, pkt->size);
+ set_dma_addr1(ep->indma, virt_to_phys(pkt->payload));
+ enable_dma_buffer1(ep->indma); // reenable
+ } else {
+ set_dma_count0(ep->indma, pkt->size);
+ set_dma_addr0(ep->indma, virt_to_phys(pkt->payload));
+ enable_dma_buffer0(ep->indma); // reenable
+ }
+ if (dma_halted(ep->indma))
+ start_dma(ep->indma);
+}
+
+
+/*
+ * This routine is called when a packet in the inlist has been
+ * completed. Frees the completed packet and starts sending the
+ * next. EP spinlock must be held when calling.
+ */
+static usbdev_pkt_t *
+send_packet_complete(endpoint_t * ep)
+{
+ usbdev_pkt_t *pkt = unlink_head(&ep->inlist);
+
+ if (pkt) {
+ pkt->status =
+ (au_readl(ep->reg->ctrl_stat) & USBDEV_CS_NAK) ?
+ PKT_STATUS_NAK : PKT_STATUS_ACK;
+
+ vdbg("%s: ep%d, %s pkt=%p, list count=%d", __FUNCTION__,
+ ep->address, (pkt->status & PKT_STATUS_NAK) ?
+ "NAK" : "ACK", pkt, ep->inlist.count);
+ }
+
+ /*
+ * The write fifo should already be drained if things are
+ * working right, but flush it anyway just in case.
+ */
+ flush_write_fifo(ep);
+
+ // begin transmitting next packet in the inlist
+ if (ep->inlist.count) {
+ kickstart_send_packet(ep);
+ }
+
+ return pkt;
+}
+
+/*
+ * Add a new packet to the tail of the given ep's packet
+ * inlist. The transmit complete interrupt frees packets from
+ * the head of this list. EP spinlock must be held when calling.
+ */
+static int
+send_packet(struct usb_dev* dev, usbdev_pkt_t *pkt, int async)
+{
+ pkt_list_t *list;
+ endpoint_t* ep;
+
+ if (!pkt || !(ep = epaddr_to_ep(dev, pkt->ep_addr)))
+ return -EINVAL;
+
+ if (!pkt->size)
+ return 0;
+
+ list = &ep->inlist;
+
+ if (!async && list->count) {
+ halt_dma(ep->indma);
+ flush_pkt_list(list);
+ }
+
+ link_tail(ep, list, pkt);
+
+ vdbg("%s: ep%d, pkt=%p, size=%d, list count=%d", __FUNCTION__,
+ ep->address, pkt, pkt->size, list->count);
+
+ if (list->count == 1) {
+ /*
+ * if the packet count is one, it means the list was empty,
+ * and no more data will go out this ep until we kick-start
+ * it again.
+ */
+ kickstart_send_packet(ep);
+ }
+
+ return pkt->size;
+}
+
+/*
+ * This routine is called to restart reception of a packet.
+ * EP spinlock must be held when calling.
+ */
+static void
+kickstart_receive_packet(endpoint_t * ep)
+{
+ usbdev_pkt_t *pkt;
+
+ // get and link a new packet for next reception
+ if (!(pkt = add_packet(ep, &ep->outlist, ep->max_pkt_size))) {
+ err("%s: could not alloc new packet", __FUNCTION__);
+ return;
+ }
+
+ if (get_dma_active_buffer(ep->outdma) == 1) {
+ clear_dma_done1(ep->outdma);
+ set_dma_count1(ep->outdma, ep->max_pkt_size);
+ set_dma_count0(ep->outdma, 0);
+ set_dma_addr1(ep->outdma, virt_to_phys(pkt->payload));
+ enable_dma_buffer1(ep->outdma); // reenable
+ } else {
+ clear_dma_done0(ep->outdma);
+ set_dma_count0(ep->outdma, ep->max_pkt_size);
+ set_dma_count1(ep->outdma, 0);
+ set_dma_addr0(ep->outdma, virt_to_phys(pkt->payload));
+ enable_dma_buffer0(ep->outdma); // reenable
+ }
+ if (dma_halted(ep->outdma))
+ start_dma(ep->outdma);
+}
+
+
+/*
+ * This routine is called when a packet in the outlist has been
+ * completed (received) and we need to prepare for a new packet
+ * to be received. Halts DMA and computes the packet size from the
+ * remaining DMA counter. Then prepares a new packet for reception
+ * and restarts DMA. FIXME: what if another packet comes in
+ * on top of the completed packet? Counter would be wrong.
+ * EP spinlock must be held when calling.
+ */
+static usbdev_pkt_t *
+receive_packet_complete(endpoint_t * ep)
+{
+ usbdev_pkt_t *pkt = ep->outlist.tail;
+ u32 cs;
+
+ halt_dma(ep->outdma);
+
+ cs = au_readl(ep->reg->ctrl_stat);
+
+ if (!pkt)
+ return NULL;
+
+ pkt->size = ep->max_pkt_size - get_dma_residue(ep->outdma);
+ if (pkt->size)
+ dma_cache_inv((unsigned long)pkt->payload, pkt->size);
+ /*
+ * need to pull out any remaining bytes in the FIFO.
+ */
+ endpoint_fifo_read(ep);
+ /*
+ * should be drained now, but flush anyway just in case.
+ */
+ flush_read_fifo(ep);
+
+ pkt->status = (cs & USBDEV_CS_NAK) ? PKT_STATUS_NAK : PKT_STATUS_ACK;
+ if (ep->address == 0 && (cs & USBDEV_CS_SU))
+ pkt->status |= PKT_STATUS_SU;
+
+ vdbg("%s: ep%d, %s pkt=%p, size=%d", __FUNCTION__,
+ ep->address, (pkt->status & PKT_STATUS_NAK) ?
+ "NAK" : "ACK", pkt, pkt->size);
+
+ kickstart_receive_packet(ep);
+
+ return pkt;
+}
+
+
+/*
+ ****************************************************************************
+ * Here starts the standard device request handlers. They are
+ * all called by do_setup() via a table of function pointers.
+ ****************************************************************************
+ */
+
+static ep0_stage_t
+do_get_status(struct usb_dev* dev, struct usb_ctrlrequest* setup)
+{
+ switch (setup->bRequestType) {
+ case 0x80: // Device
+ // FIXME: send device status
+ break;
+ case 0x81: // Interface
+ // FIXME: send interface status
+ break;
+ case 0x82: // End Point
+ // FIXME: send endpoint status
+ break;
+ default:
+ // Invalid Command
+ endpoint_stall(&dev->ep[0]); // Stall End Point 0
+ break;
+ }
+
+ return STATUS_STAGE;
+}
+
+static ep0_stage_t
+do_clear_feature(struct usb_dev* dev, struct usb_ctrlrequest* setup)
+{
+ switch (setup->bRequestType) {
+ case 0x00: // Device
+ if ((le16_to_cpu(setup->wValue) & 0xff) == 1)
+ dev->remote_wakeup_en = 0;
+ else
+ endpoint_stall(&dev->ep[0]);
+ break;
+ case 0x02: // End Point
+ if ((le16_to_cpu(setup->wValue) & 0xff) == 0) {
+ endpoint_t *ep =
+ epaddr_to_ep(dev,
+ le16_to_cpu(setup->wIndex) & 0xff);
+
+ endpoint_unstall(ep);
+ endpoint_reset_datatoggle(ep);
+ } else
+ endpoint_stall(&dev->ep[0]);
+ break;
+ }
+
+ return SETUP_STAGE;
+}
+
+static ep0_stage_t
+do_reserved(struct usb_dev* dev, struct usb_ctrlrequest* setup)
+{
+ // Invalid request, stall End Point 0
+ endpoint_stall(&dev->ep[0]);
+ return SETUP_STAGE;
+}
+
+static ep0_stage_t
+do_set_feature(struct usb_dev* dev, struct usb_ctrlrequest* setup)
+{
+ switch (setup->bRequestType) {
+ case 0x00: // Device
+ if ((le16_to_cpu(setup->wValue) & 0xff) == 1)
+ dev->remote_wakeup_en = 1;
+ else
+ endpoint_stall(&dev->ep[0]);
+ break;
+ case 0x02: // End Point
+ if ((le16_to_cpu(setup->wValue) & 0xff) == 0) {
+ endpoint_t *ep =
+ epaddr_to_ep(dev,
+ le16_to_cpu(setup->wIndex) & 0xff);
+
+ endpoint_stall(ep);
+ } else
+ endpoint_stall(&dev->ep[0]);
+ break;
+ }
+
+ return SETUP_STAGE;
+}
+
+static ep0_stage_t
+do_set_address(struct usb_dev* dev, struct usb_ctrlrequest* setup)
+{
+ int new_state = dev->state;
+ int new_addr = le16_to_cpu(setup->wValue);
+
+ dbg("%s: our address=%d", __FUNCTION__, new_addr);
+
+ if (new_addr > 127) {
+ // usb spec doesn't tell us what to do, so just go to
+ // default state
+ new_state = DEFAULT;
+ dev->address = 0;
+ } else if (dev->address != new_addr) {
+ dev->address = new_addr;
+ new_state = ADDRESS;
+ }
+
+ if (dev->state != new_state) {
+ dev->state = new_state;
+ /* inform function layer of usbdev state change */
+ dev->func_cb(CB_NEW_STATE, dev->state, dev->cb_data);
+ }
+
+ return SETUP_STAGE;
+}
+
+static ep0_stage_t
+do_get_descriptor(struct usb_dev* dev, struct usb_ctrlrequest* setup)
+{
+ int strnum, desc_len = le16_to_cpu(setup->wLength);
+
+ switch (le16_to_cpu(setup->wValue) >> 8) {
+ case USB_DT_DEVICE:
+ // send device descriptor!
+ desc_len = desc_len > dev->dev_desc->bLength ?
+ dev->dev_desc->bLength : desc_len;
+ dbg("sending device desc, size=%d", desc_len);
+ send_packet(dev, alloc_packet(&dev->ep[0], desc_len,
+ dev->dev_desc), 0);
+ break;
+ case USB_DT_CONFIG:
+ // If the config descr index in low-byte of
+ // setup->wValue is valid, send config descr,
+ // otherwise stall ep0.
+ if ((le16_to_cpu(setup->wValue) & 0xff) == 0) {
+ // send config descriptor!
+ if (desc_len <= USB_DT_CONFIG_SIZE) {
+ dbg("sending partial config desc, size=%d",
+ desc_len);
+ send_packet(dev,
+ alloc_packet(&dev->ep[0],
+ desc_len,
+ dev->conf_desc),
+ 0);
+ } else {
+ int len = le16_to_cpu(dev->conf_desc->wTotalLength);
+ dbg("sending whole config desc,"
+ " size=%d, our size=%d", desc_len, len);
+ desc_len = desc_len > len ? len : desc_len;
+ send_packet(dev,
+ alloc_packet(&dev->ep[0],
+ desc_len,
+ dev->full_conf_desc),
+ 0);
+ }
+ } else
+ endpoint_stall(&dev->ep[0]);
+ break;
+ case USB_DT_STRING:
+ // If the string descr index in low-byte of setup->wValue
+ // is valid, send string descr, otherwise stall ep0.
+ strnum = le16_to_cpu(setup->wValue) & 0xff;
+ if (strnum >= 0 && strnum < 6) {
+ struct usb_string_descriptor *desc =
+ dev->str_desc[strnum];
+ desc_len = desc_len > desc->bLength ?
+ desc->bLength : desc_len;
+ dbg("sending string desc %d", strnum);
+ send_packet(dev,
+ alloc_packet(&dev->ep[0], desc_len,
+ desc), 0);
+ } else
+ endpoint_stall(&dev->ep[0]);
+ break;
+ default:
+ // Invalid request
+ err("invalid get desc=%d, stalled",
+ le16_to_cpu(setup->wValue) >> 8);
+ endpoint_stall(&dev->ep[0]); // Stall endpoint 0
+ break;
+ }
+
+ return STATUS_STAGE;
+}
+
+static ep0_stage_t
+do_set_descriptor(struct usb_dev* dev, struct usb_ctrlrequest* setup)
+{
+ // TODO: implement
+ // there will be an OUT data stage (the descriptor to set)
+ return DATA_STAGE;
+}
+
+static ep0_stage_t
+do_get_configuration(struct usb_dev* dev, struct usb_ctrlrequest* setup)
+{
+ // send dev->configuration
+ dbg("sending config");
+ send_packet(dev, alloc_packet(&dev->ep[0], 1, &dev->configuration),
+ 0);
+ return STATUS_STAGE;
+}
+
+static ep0_stage_t
+do_set_configuration(struct usb_dev* dev, struct usb_ctrlrequest* setup)
+{
+ // set active config to low-byte of setup->wValue
+ dev->configuration = le16_to_cpu(setup->wValue) & 0xff;
+ dbg("set config, config=%d", dev->configuration);
+ if (!dev->configuration && dev->state > DEFAULT) {
+ dev->state = ADDRESS;
+ /* inform function layer of usbdev state change */
+ dev->func_cb(CB_NEW_STATE, dev->state, dev->cb_data);
+ } else if (dev->configuration == 1) {
+ dev->state = CONFIGURED;
+ /* inform function layer of usbdev state change */
+ dev->func_cb(CB_NEW_STATE, dev->state, dev->cb_data);
+ } else {
+ // FIXME: "respond with request error" - how?
+ }
+
+ return SETUP_STAGE;
+}
+
+static ep0_stage_t
+do_get_interface(struct usb_dev* dev, struct usb_ctrlrequest* setup)
+{
+ // interface must be zero.
+ if ((le16_to_cpu(setup->wIndex) & 0xff) || dev->state == ADDRESS) {
+ // FIXME: respond with "request error". how?
+ } else if (dev->state == CONFIGURED) {
+ // send dev->alternate_setting
+ dbg("sending alt setting");
+ send_packet(dev, alloc_packet(&dev->ep[0], 1,
+ &dev->alternate_setting), 0);
+ }
+
+ return STATUS_STAGE;
+
+}
+
+static ep0_stage_t
+do_set_interface(struct usb_dev* dev, struct usb_ctrlrequest* setup)
+{
+ if (dev->state == ADDRESS) {
+ // FIXME: respond with "request error". how?
+ } else if (dev->state == CONFIGURED) {
+ dev->interface = le16_to_cpu(setup->wIndex) & 0xff;
+ dev->alternate_setting =
+ le16_to_cpu(setup->wValue) & 0xff;
+ // interface and alternate_setting must be zero
+ if (dev->interface || dev->alternate_setting) {
+ // FIXME: respond with "request error". how?
+ }
+ }
+
+ return SETUP_STAGE;
+}
+
+static ep0_stage_t
+do_synch_frame(struct usb_dev* dev, struct usb_ctrlrequest* setup)
+{
+ // TODO
+ return SETUP_STAGE;
+}
+
+typedef ep0_stage_t (*req_method_t)(struct usb_dev* dev,
+ struct usb_ctrlrequest* setup);
+
+
+/* Table of the standard device request handlers */
+static const req_method_t req_method[] = {
+ do_get_status,
+ do_clear_feature,
+ do_reserved,
+ do_set_feature,
+ do_reserved,
+ do_set_address,
+ do_get_descriptor,
+ do_set_descriptor,
+ do_get_configuration,
+ do_set_configuration,
+ do_get_interface,
+ do_set_interface,
+ do_synch_frame
+};
+
+
+// SETUP packet request dispatcher
+static void
+do_setup (struct usb_dev* dev, struct usb_ctrlrequest* setup)
+{
+ req_method_t m;
+
+ dbg("%s: req %d %s", __FUNCTION__, setup->bRequestType,
+ get_std_req_name(setup->bRequestType));
+
+ if ((setup->bRequestType & USB_TYPE_MASK) != USB_TYPE_STANDARD ||
+ (setup->bRequestType & USB_RECIP_MASK) != USB_RECIP_DEVICE) {
+ err("%s: invalid requesttype 0x%02x", __FUNCTION__,
+ setup->bRequestType);
+ return;
+ }
+
+ if ((setup->bRequestType & 0x80) == USB_DIR_OUT && setup->wLength)
+ dbg("%s: OUT phase! length=%d", __FUNCTION__, setup->wLength);
+
+ if (setup->bRequestType < sizeof(req_method)/sizeof(req_method_t))
+ m = req_method[setup->bRequestType];
+ else
+ m = do_reserved;
+
+ dev->ep0_stage = (*m)(dev, setup);
+}
+
+/*
+ * A SETUP, DATA0, or DATA1 packet has been received
+ * on the default control endpoint's fifo.
+ */
+static void
+process_ep0_receive (struct usb_dev* dev)
+{
+ endpoint_t *ep0 = &dev->ep[0];
+ usbdev_pkt_t *pkt;
+
+ spin_lock(&ep0->lock);
+
+ // complete packet and prepare a new packet
+ pkt = receive_packet_complete(ep0);
+ if (!pkt) {
+ // FIXME: should put a warn/err here.
+ spin_unlock(&ep0->lock);
+ return;
+ }
+
+ // unlink immediately from endpoint.
+ unlink_head(&ep0->outlist);
+
+ // override current stage if h/w says it's a setup packet
+ if (pkt->status & PKT_STATUS_SU)
+ dev->ep0_stage = SETUP_STAGE;
+
+ switch (dev->ep0_stage) {
+ case SETUP_STAGE:
+ vdbg("SU bit is %s in setup stage",
+ (pkt->status & PKT_STATUS_SU) ? "set" : "not set");
+
+ if (pkt->size == sizeof(struct usb_ctrlrequest)) {
+#ifdef VDEBUG
+ if (pkt->status & PKT_STATUS_ACK)
+ vdbg("received SETUP");
+ else
+ vdbg("received NAK SETUP");
+#endif
+ do_setup(dev, (struct usb_ctrlrequest*)pkt->payload);
+ } else
+ err("%s: wrong size SETUP received", __FUNCTION__);
+ break;
+ case DATA_STAGE:
+ /*
+ * this setup has an OUT data stage. Of the standard
+ * device requests, only set_descriptor has this stage,
+ * so this packet is that descriptor. TODO: drop it for
+ * now, set_descriptor not implemented.
+ *
+ * Need to place a byte in the write FIFO here, to prepare
+ * to send a zero-length DATA ack packet to the host in the
+ * STATUS stage.
+ */
+ au_writel(0, ep0->reg->write_fifo);
+ dbg("received OUT stage DATAx on EP0, size=%d", pkt->size);
+ dev->ep0_stage = SETUP_STAGE;
+ break;
+ case STATUS_STAGE:
+ // this setup had an IN data stage, and host is ACK'ing
+ // the packet we sent during that stage.
+ if (pkt->size != 0)
+ warn("received non-zero ACK on EP0??");
+#ifdef VDEBUG
+ else
+ vdbg("received ACK on EP0");
+#endif
+ dev->ep0_stage = SETUP_STAGE;
+ break;
+ }
+
+ spin_unlock(&ep0->lock);
+ // we're done processing the packet, free it
+ kfree(pkt);
+}
+
+
+/*
+ * A DATA0/1 packet has been received on one of the OUT endpoints (4 or 5)
+ */
+static void
+process_ep_receive (struct usb_dev* dev, endpoint_t *ep)
+{
+ usbdev_pkt_t *pkt;
+
+ spin_lock(&ep->lock);
+ pkt = receive_packet_complete(ep);
+ spin_unlock(&ep->lock);
+
+ dev->func_cb(CB_PKT_COMPLETE, (unsigned long)pkt, dev->cb_data);
+}
+
+
+
+/* This ISR handles the receive complete and suspend events */
+static void
+req_sus_intr (int irq, void *dev_id, struct pt_regs *regs)
+{
+ struct usb_dev *dev = (struct usb_dev *) dev_id;
+ u32 status;
+
+ status = au_readl(USBD_INTSTAT);
+ au_writel(status, USBD_INTSTAT); // ack'em
+
+ if (status & (1<<0))
+ process_ep0_receive(dev);
+ if (status & (1<<4))
+ process_ep_receive(dev, &dev->ep[4]);
+ if (status & (1<<5))
+ process_ep_receive(dev, &dev->ep[5]);
+}
+
+
+/* This ISR handles the DMA done events on EP0 */
+static void
+dma_done_ep0_intr(int irq, void *dev_id, struct pt_regs *regs)
+{
+ struct usb_dev *dev = (struct usb_dev *) dev_id;
+ usbdev_pkt_t* pkt;
+ endpoint_t *ep0 = &dev->ep[0];
+ u32 cs0, buff_done;
+
+ spin_lock(&ep0->lock);
+ cs0 = au_readl(ep0->reg->ctrl_stat);
+
+ // first check packet transmit done
+ if ((buff_done = get_dma_buffer_done(ep0->indma)) != 0) {
+ // transmitted a DATAx packet during DATA stage
+ // on control endpoint 0
+ // clear DMA done bit
+ if (buff_done & DMA_D0)
+ clear_dma_done0(ep0->indma);
+ if (buff_done & DMA_D1)
+ clear_dma_done1(ep0->indma);
+
+ pkt = send_packet_complete(ep0);
+ if (pkt)
+ kfree(pkt);
+ }
+
+ /*
+ * Now check packet receive done. Shouldn't get these,
+ * the receive packet complete intr should happen
+ * before the DMA done intr occurs.
+ */
+ if ((buff_done = get_dma_buffer_done(ep0->outdma)) != 0) {
+ // clear DMA done bit
+ if (buff_done & DMA_D0)
+ clear_dma_done0(ep0->outdma);
+ if (buff_done & DMA_D1)
+ clear_dma_done1(ep0->outdma);
+
+ //process_ep0_receive(dev);
+ }
+
+ spin_unlock(&ep0->lock);
+}
+
+/* This ISR handles the DMA done events on endpoints 2,3,4,5 */
+static void
+dma_done_ep_intr(int irq, void *dev_id, struct pt_regs *regs)
+{
+ struct usb_dev *dev = (struct usb_dev *) dev_id;
+ int i;
+
+ for (i = 2; i < 6; i++) {
+ u32 buff_done;
+ usbdev_pkt_t* pkt;
+ endpoint_t *ep = &dev->ep[i];
+
+ if (!ep->active) continue;
+
+ spin_lock(&ep->lock);
+
+ if (ep->direction == USB_DIR_IN) {
+ buff_done = get_dma_buffer_done(ep->indma);
+ if (buff_done != 0) {
+ // transmitted a DATAx pkt on the IN ep
+ // clear DMA done bit
+ if (buff_done & DMA_D0)
+ clear_dma_done0(ep->indma);
+ if (buff_done & DMA_D1)
+ clear_dma_done1(ep->indma);
+
+ pkt = send_packet_complete(ep);
+
+ spin_unlock(&ep->lock);
+ dev->func_cb(CB_PKT_COMPLETE,
+ (unsigned long)pkt,
+ dev->cb_data);
+ spin_lock(&ep->lock);
+ }
+ } else {
+ /*
+ * Check packet receive done (OUT ep). Shouldn't get
+ * these, the rx packet complete intr should happen
+ * before the DMA done intr occurs.
+ */
+ buff_done = get_dma_buffer_done(ep->outdma);
+ if (buff_done != 0) {
+ // received a DATAx pkt on the OUT ep
+ // clear DMA done bit
+ if (buff_done & DMA_D0)
+ clear_dma_done0(ep->outdma);
+ if (buff_done & DMA_D1)
+ clear_dma_done1(ep->outdma);
+
+ //process_ep_receive(dev, ep);
+ }
+ }
+
+ spin_unlock(&ep->lock);
+ }
+}
+
+
+/***************************************************************************
+ * Here begins the external interface functions
+ ***************************************************************************
+ */
+
+/*
+ * allocate a new packet
+ */
+int
+usbdev_alloc_packet(int ep_addr, int data_size, usbdev_pkt_t** pkt)
+{
+ endpoint_t * ep = epaddr_to_ep(&usbdev, ep_addr);
+ usbdev_pkt_t* lpkt = NULL;
+
+ if (!ep || !ep->active || ep->address < 2)
+ return -ENODEV;
+ if (data_size > ep->max_pkt_size)
+ return -EINVAL;
+
+ lpkt = *pkt = alloc_packet(ep, data_size, NULL);
+ if (!lpkt)
+ return -ENOMEM;
+ return 0;
+}
+
+
+/*
+ * packet send
+ */
+int
+usbdev_send_packet(int ep_addr, usbdev_pkt_t * pkt)
+{
+ unsigned long flags;
+ int count;
+ endpoint_t * ep;
+
+ if (!pkt || !(ep = epaddr_to_ep(&usbdev, pkt->ep_addr)) ||
+ !ep->active || ep->address < 2)
+ return -ENODEV;
+ if (ep->direction != USB_DIR_IN)
+ return -EINVAL;
+
+ spin_lock_irqsave(&ep->lock, flags);
+ count = send_packet(&usbdev, pkt, 1);
+ spin_unlock_irqrestore(&ep->lock, flags);
+
+ return count;
+}
+
+/*
+ * packet receive
+ */
+int
+usbdev_receive_packet(int ep_addr, usbdev_pkt_t** pkt)
+{
+ unsigned long flags;
+ usbdev_pkt_t* lpkt = NULL;
+ endpoint_t *ep = epaddr_to_ep(&usbdev, ep_addr);
+
+ if (!ep || !ep->active || ep->address < 2)
+ return -ENODEV;
+ if (ep->direction != USB_DIR_OUT)
+ return -EINVAL;
+
+ spin_lock_irqsave(&ep->lock, flags);
+ if (ep->outlist.count > 1)
+ lpkt = unlink_head(&ep->outlist);
+ spin_unlock_irqrestore(&ep->lock, flags);
+
+ if (!lpkt) {
+ /* no packet available */
+ *pkt = NULL;
+ return -ENODATA;
+ }
+
+ *pkt = lpkt;
+
+ return lpkt->size;
+}
+
+
+/*
+ * return total queued byte count on the endpoint.
+ */
+int
+usbdev_get_byte_count(int ep_addr)
+{
+ unsigned long flags;
+ pkt_list_t *list;
+ usbdev_pkt_t *scan;
+ int count = 0;
+ endpoint_t * ep = epaddr_to_ep(&usbdev, ep_addr);
+
+ if (!ep || !ep->active || ep->address < 2)
+ return -ENODEV;
+
+ if (ep->direction == USB_DIR_IN) {
+ list = &ep->inlist;
+
+ spin_lock_irqsave(&ep->lock, flags);
+ for (scan = list->head; scan; scan = scan->next)
+ count += scan->size;
+ spin_unlock_irqrestore(&ep->lock, flags);
+ } else {
+ list = &ep->outlist;
+
+ spin_lock_irqsave(&ep->lock, flags);
+ if (list->count > 1) {
+ for (scan = list->head; scan != list->tail;
+ scan = scan->next)
+ count += scan->size;
+ }
+ spin_unlock_irqrestore(&ep->lock, flags);
+ }
+
+ return count;
+}
+
+
+void
+usbdev_exit(void)
+{
+ endpoint_t *ep;
+ int i;
+
+ au_writel(0, USBD_INTEN); // disable usb dev ints
+ au_writel(0, USBD_ENABLE); // disable usb dev
+
+ free_irq(AU1000_USB_DEV_REQ_INT, &usbdev);
+ free_irq(AU1000_USB_DEV_SUS_INT, &usbdev);
+
+ // free all control endpoint resources
+ ep = &usbdev.ep[0];
+ free_au1000_dma(ep->indma);
+ free_au1000_dma(ep->outdma);
+ endpoint_flush(ep);
+
+ // free ep resources
+ for (i = 2; i < 6; i++) {
+ ep = &usbdev.ep[i];
+ if (!ep->active) continue;
+
+ if (ep->direction == USB_DIR_IN) {
+ free_au1000_dma(ep->indma);
+ } else {
+ free_au1000_dma(ep->outdma);
+ }
+ endpoint_flush(ep);
+ }
+
+ if (usbdev.full_conf_desc)
+ kfree(usbdev.full_conf_desc);
+}
+
+int
+usbdev_init(struct usb_device_descriptor* dev_desc,
+ struct usb_config_descriptor* config_desc,
+ struct usb_interface_descriptor* if_desc,
+ struct usb_endpoint_descriptor* ep_desc,
+ struct usb_string_descriptor* str_desc[],
+ void (*cb)(usbdev_cb_type_t, unsigned long, void *),
+ void* cb_data)
+{
+ endpoint_t *ep0;
+ int i, ret=0;
+ u8* fcd;
+
+ if (dev_desc->bNumConfigurations > 1 ||
+ config_desc->bNumInterfaces > 1 ||
+ if_desc->bNumEndpoints > 4) {
+ err("Only one config, one i/f, and no more "
+ "than 4 ep's allowed");
+ ret = -EINVAL;
+ goto out;
+ }
+
+ if (!cb) {
+ err("Function-layer callback required");
+ ret = -EINVAL;
+ goto out;
+ }
+
+ if (dev_desc->bMaxPacketSize0 != USBDEV_EP0_MAX_PACKET_SIZE) {
+ warn("EP0 Max Packet size must be %d",
+ USBDEV_EP0_MAX_PACKET_SIZE);
+ dev_desc->bMaxPacketSize0 = USBDEV_EP0_MAX_PACKET_SIZE;
+ }
+
+ memset(&usbdev, 0, sizeof(struct usb_dev));
+
+ usbdev.state = DEFAULT;
+ usbdev.dev_desc = dev_desc;
+ usbdev.if_desc = if_desc;
+ usbdev.conf_desc = config_desc;
+ for (i=0; i<6; i++)
+ usbdev.str_desc[i] = str_desc[i];
+ usbdev.func_cb = cb;
+ usbdev.cb_data = cb_data;
+
+ /* Initialize default control endpoint */
+ ep0 = &usbdev.ep[0];
+ ep0->active = 1;
+ ep0->type = CONTROL_EP;
+ ep0->max_pkt_size = USBDEV_EP0_MAX_PACKET_SIZE;
+ spin_lock_init(&ep0->lock);
+ ep0->desc = NULL; // ep0 has no descriptor
+ ep0->address = 0;
+ ep0->direction = 0;
+ ep0->reg = &ep_reg[0];
+
+ /* Initialize the other requested endpoints */
+ for (i = 0; i < if_desc->bNumEndpoints; i++) {
+ struct usb_endpoint_descriptor* epd = &ep_desc[i];
+ endpoint_t *ep;
+
+ if ((epd->bEndpointAddress & 0x80) == USB_DIR_IN) {
+ ep = &usbdev.ep[2];
+ ep->address = 2;
+ if (ep->active) {
+ ep = &usbdev.ep[3];
+ ep->address = 3;
+ if (ep->active) {
+ err("too many IN ep's requested");
+ ret = -ENODEV;
+ goto out;
+ }
+ }
+ } else {
+ ep = &usbdev.ep[4];
+ ep->address = 4;
+ if (ep->active) {
+ ep = &usbdev.ep[5];
+ ep->address = 5;
+ if (ep->active) {
+ err("too many OUT ep's requested");
+ ret = -ENODEV;
+ goto out;
+ }
+ }
+ }
+
+ ep->active = 1;
+ epd->bEndpointAddress &= ~0x0f;
+ epd->bEndpointAddress |= (u8)ep->address;
+ ep->direction = epd->bEndpointAddress & 0x80;
+ ep->type = epd->bmAttributes & 0x03;
+ ep->max_pkt_size = le16_to_cpu(epd->wMaxPacketSize);
+ spin_lock_init(&ep->lock);
+ ep->desc = epd;
+ ep->reg = &ep_reg[ep->address];
+ }
+
+ /*
+ * initialize the full config descriptor
+ */
+ usbdev.full_conf_desc = fcd = kmalloc(le16_to_cpu(config_desc->wTotalLength),
+ ALLOC_FLAGS);
+ if (!fcd) {
+ err("failed to alloc full config descriptor");
+ ret = -ENOMEM;
+ goto out;
+ }
+
+ memcpy(fcd, config_desc, USB_DT_CONFIG_SIZE);
+ fcd += USB_DT_CONFIG_SIZE;
+ memcpy(fcd, if_desc, USB_DT_INTERFACE_SIZE);
+ fcd += USB_DT_INTERFACE_SIZE;
+ for (i = 0; i < if_desc->bNumEndpoints; i++) {
+ memcpy(fcd, &ep_desc[i], USB_DT_ENDPOINT_SIZE);
+ fcd += USB_DT_ENDPOINT_SIZE;
+ }
+
+ /* Now we're ready to enable the controller */
+ au_writel(0x0002, USBD_ENABLE);
+ udelay(100);
+ au_writel(0x0003, USBD_ENABLE);
+ udelay(100);
+
+ /* build and send config table based on ep descriptors */
+ for (i = 0; i < 6; i++) {
+ endpoint_t *ep;
+ if (i == 1)
+ continue; // skip dummy ep
+ ep = &usbdev.ep[i];
+ if (ep->active) {
+ au_writel((ep->address << 4) | 0x04, USBD_CONFIG);
+ au_writel(((ep->max_pkt_size & 0x380) >> 7) |
+ (ep->direction >> 4) | (ep->type << 4),
+ USBD_CONFIG);
+ au_writel((ep->max_pkt_size & 0x7f) << 1, USBD_CONFIG);
+ au_writel(0x00, USBD_CONFIG);
+ au_writel(ep->address, USBD_CONFIG);
+ } else {
+ u8 dir = (i==2 || i==3) ? DIR_IN : DIR_OUT;
+ au_writel((i << 4) | 0x04, USBD_CONFIG);
+ au_writel(((16 & 0x380) >> 7) | dir |
+ (BULK_EP << 4), USBD_CONFIG);
+ au_writel((16 & 0x7f) << 1, USBD_CONFIG);
+ au_writel(0x00, USBD_CONFIG);
+ au_writel(i, USBD_CONFIG);
+ }
+ }
+
+ /*
+ * Enable Receive FIFO Complete interrupts only. Transmit
+ * complete is being handled by the DMA done interrupts.
+ */
+ au_writel(0x31, USBD_INTEN);
+
+ /*
+ * Controller is now enabled, request DMA and IRQ
+ * resources.
+ */
+
+ /* request the USB device transfer complete interrupt */
+ if (request_irq(AU1000_USB_DEV_REQ_INT, req_sus_intr, SA_INTERRUPT,
+ "USBdev req", &usbdev)) {
+ err("Can't get device request intr");
+ ret = -ENXIO;
+ goto out;
+ }
+ /* request the USB device suspend interrupt */
+ if (request_irq(AU1000_USB_DEV_SUS_INT, req_sus_intr, SA_INTERRUPT,
+ "USBdev sus", &usbdev)) {
+ err("Can't get device suspend intr");
+ ret = -ENXIO;
+ goto out;
+ }
+
+ /* Request EP0 DMA and IRQ */
+ if ((ep0->indma = request_au1000_dma(ep_dma_id[0].id,
+ ep_dma_id[0].str,
+ dma_done_ep0_intr,
+ SA_INTERRUPT,
+ &usbdev)) < 0) {
+ err("Can't get %s DMA", ep_dma_id[0].str);
+ ret = -ENXIO;
+ goto out;
+ }
+ if ((ep0->outdma = request_au1000_dma(ep_dma_id[1].id,
+ ep_dma_id[1].str,
+ NULL, 0, NULL)) < 0) {
+ err("Can't get %s DMA", ep_dma_id[1].str);
+ ret = -ENXIO;
+ goto out;
+ }
+
+ // Flush the ep0 buffers and FIFOs
+ endpoint_flush(ep0);
+ // start packet reception on ep0
+ kickstart_receive_packet(ep0);
+
+ /* Request DMA and IRQ for the other endpoints */
+ for (i = 2; i < 6; i++) {
+ endpoint_t *ep = &usbdev.ep[i];
+ if (!ep->active)
+ continue;
+
+ // Flush the endpoint buffers and FIFOs
+ endpoint_flush(ep);
+
+ if (ep->direction == USB_DIR_IN) {
+ ep->indma =
+ request_au1000_dma(ep_dma_id[ep->address].id,
+ ep_dma_id[ep->address].str,
+ dma_done_ep_intr,
+ SA_INTERRUPT,
+ &usbdev);
+ if (ep->indma < 0) {
+ err("Can't get %s DMA",
+ ep_dma_id[ep->address].str);
+ ret = -ENXIO;
+ goto out;
+ }
+ } else {
+ ep->outdma =
+ request_au1000_dma(ep_dma_id[ep->address].id,
+ ep_dma_id[ep->address].str,
+ NULL, 0, NULL);
+ if (ep->outdma < 0) {
+ err("Can't get %s DMA",
+ ep_dma_id[ep->address].str);
+ ret = -ENXIO;
+ goto out;
+ }
+
+ // start packet reception on OUT endpoint
+ kickstart_receive_packet(ep);
+ }
+ }
+
+ out:
+ if (ret)
+ usbdev_exit();
+ return ret;
+}
+
+EXPORT_SYMBOL(usbdev_init);
+EXPORT_SYMBOL(usbdev_exit);
+EXPORT_SYMBOL(usbdev_alloc_packet);
+EXPORT_SYMBOL(usbdev_receive_packet);
+EXPORT_SYMBOL(usbdev_send_packet);
+EXPORT_SYMBOL(usbdev_get_byte_count);
generated by cgit v1.2.3 (git 2.25.1) at 2024-12-15 18:01:42 +0000