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authorSergei Shtylyov <sshtylyov@ru.mvista.com>2007-02-07 18:18:05 +0100
committerBartlomiej Zolnierkiewicz <bzolnier@gmail.com>2007-02-07 18:18:05 +0100
commitabc4ad4c6b3c6a51a0aa633e3d3fbc80b0ecabfe (patch)
tree45adfdd195a639672bde7d61dad4c3bd8a42ec3e /arch/mips/au1000/db1x00
parentb4586715d7944dfbcb2b6b76a0098413cf3222e4 (diff)
hpt366: cache channel's MCR address
Begin the real driver redesign. For the starters: - cache the offset of the IDE channel's MISC. control registers which are used throughout the driver in hwif->select_data; - only touch the relevant MCR when detecting the cable type on HPT374's function 1; - make HPT36x's speedproc handler look the same way as HPT37x ones; fix the PIO timing register mask for HPT37x. - rename all the HPT3xx register related variables consistently; clean up the whitespace. Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com> Cc: Alan Cox <alan@lxorguk.ukuu.org.uk> Signed-off-by: Andrew Morton <akpm@osdl.org> Signed-off-by: Bartlomiej Zolnierkiewicz <bzolnier@gmail.com>
Diffstat (limited to 'arch/mips/au1000/db1x00')
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