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| author | Takashi Iwai <tiwai@suse.de> | 2009-03-17 09:28:13 +0100 |
|---|---|---|
| committer | Takashi Iwai <tiwai@suse.de> | 2009-03-17 09:28:13 +0100 |
| commit | 37ba1b62836d2440980cf553c49556393b05c6cd (patch) | |
| tree | 3bbd9b76117d484d5a624db1b2b9ec0181c7ff55 /arch/mips/include/asm/prefetch.h | |
| parent | 1713c0d508fbbb42aa5f90039195e5ac31a50625 (diff) | |
| parent | dde332b660cf0bc2baaba678b52768a0fb6e6da2 (diff) | |
Merge branch 'fix/opl3sa2-suspend' into topic/isa-misc
Diffstat (limited to 'arch/mips/include/asm/prefetch.h')
| -rw-r--r-- | arch/mips/include/asm/prefetch.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/mips/include/asm/prefetch.h b/arch/mips/include/asm/prefetch.h index 17850834ccb..a56594f360e 100644 --- a/arch/mips/include/asm/prefetch.h +++ b/arch/mips/include/asm/prefetch.h @@ -26,7 +26,7 @@ * Pref_WriteBackInvalidate is a nop and Pref_PrepareForStore is broken in * current versions due to erratum G105. * - * VR7701 only implements the Load prefetch. + * VR5500 (including VR5701 and VR7701) only implement load prefetch. * * Finally MIPS32 and MIPS64 implement all of the following hints. */ |