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authorIngo Molnar <mingo@elte.hu>2008-10-13 10:52:30 +0200
committerIngo Molnar <mingo@elte.hu>2008-10-13 10:52:30 +0200
commitc493756e2a8a78bcaae30668317890dcfe86e7c3 (patch)
tree8fb40782e79472ed882ff2098d4dd295557278ee /arch/mips/include/asm/tlb.h
parent0d15504f16f68725e4635aa85411015d1c573b0a (diff)
parent4480f15b3306f43bbb0310d461142b4e897ca45b (diff)
Merge branch 'linus' into oprofile
Conflicts: arch/x86/kernel/apic_32.c include/linux/pci_ids.h
Diffstat (limited to 'arch/mips/include/asm/tlb.h')
-rw-r--r--arch/mips/include/asm/tlb.h23
1 files changed, 23 insertions, 0 deletions
diff --git a/arch/mips/include/asm/tlb.h b/arch/mips/include/asm/tlb.h
new file mode 100644
index 00000000000..80d9dfcf1e8
--- /dev/null
+++ b/arch/mips/include/asm/tlb.h
@@ -0,0 +1,23 @@
+#ifndef __ASM_TLB_H
+#define __ASM_TLB_H
+
+/*
+ * MIPS doesn't need any special per-pte or per-vma handling, except
+ * we need to flush cache for area to be unmapped.
+ */
+#define tlb_start_vma(tlb, vma) \
+ do { \
+ if (!tlb->fullmm) \
+ flush_cache_range(vma, vma->vm_start, vma->vm_end); \
+ } while (0)
+#define tlb_end_vma(tlb, vma) do { } while (0)
+#define __tlb_remove_tlb_entry(tlb, ptep, address) do { } while (0)
+
+/*
+ * .. because we flush the whole mm when it fills up.
+ */
+#define tlb_flush(tlb) flush_tlb_mm((tlb)->mm)
+
+#include <asm-generic/tlb.h>
+
+#endif /* __ASM_TLB_H */