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authorDavid Daney <ddaney@caviumnetworks.com>2008-12-11 15:33:32 -0800
committerRalf Baechle <ralf@linux-mips.org>2009-01-11 09:57:24 +0000
commitddcdb1b4a46915b70dce3af3a78582b3ca79cf76 (patch)
tree87ee691a1189a7861dd7749a5f601d83bbc636c7 /arch/mips/include/asm
parentbabed555695fad25820fb5fb0b5068c56e375900 (diff)
MIPS: Add SMP_ICACHE_FLUSH for the Cavium CPU family.
Signed-off-by: Tomaso Paoletti <tpaoletti@caviumnetworks.com> Signed-off-by: Paul Gortmaker <Paul.Gortmaker@windriver.com> Signed-off-by: David Daney <ddaney@caviumnetworks.com> Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/include/asm')
-rw-r--r--arch/mips/include/asm/smp.h3
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/mips/include/asm/smp.h b/arch/mips/include/asm/smp.h
index 86557b5d1b3..40e5ef1d4d2 100644
--- a/arch/mips/include/asm/smp.h
+++ b/arch/mips/include/asm/smp.h
@@ -37,6 +37,9 @@ extern int __cpu_logical_map[NR_CPUS];
#define SMP_RESCHEDULE_YOURSELF 0x1 /* XXX braindead */
#define SMP_CALL_FUNCTION 0x2
+/* Octeon - Tell another core to flush its icache */
+#define SMP_ICACHE_FLUSH 0x4
+
extern void asmlinkage smp_bootstrap(void);