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| author | Ingo Molnar <mingo@elte.hu> | 2008-07-06 14:23:39 +0200 |
|---|---|---|
| committer | Ingo Molnar <mingo@elte.hu> | 2008-07-06 14:23:39 +0200 |
| commit | 68083e05d72d94f347293d8cc0067050ba904bfa (patch) | |
| tree | 842e71365bd90866be7add181661a4039d891564 /arch/mips/kernel/cevt-txx9.c | |
| parent | 7baac8b91f9871ba8cb09af84de4ae1d86d07812 (diff) | |
| parent | b7279469d66b55119784b8b9529c99c1955fe747 (diff) | |
Merge commit 'v2.6.26-rc9' into cpus4096
Diffstat (limited to 'arch/mips/kernel/cevt-txx9.c')
| -rw-r--r-- | arch/mips/kernel/cevt-txx9.c | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/arch/mips/kernel/cevt-txx9.c b/arch/mips/kernel/cevt-txx9.c index 795cb8fb0d7..b5fc4eb412d 100644 --- a/arch/mips/kernel/cevt-txx9.c +++ b/arch/mips/kernel/cevt-txx9.c @@ -161,6 +161,9 @@ void __init txx9_tmr_init(unsigned long baseaddr) struct txx9_tmr_reg __iomem *tmrptr; tmrptr = ioremap(baseaddr, sizeof(struct txx9_tmr_reg)); + /* Start once to make CounterResetEnable effective */ + __raw_writel(TXx9_TMTCR_CRE | TXx9_TMTCR_TCE, &tmrptr->tcr); + /* Stop and reset the counter */ __raw_writel(TXx9_TMTCR_CRE, &tmrptr->tcr); __raw_writel(0, &tmrptr->tisr); __raw_writel(0xffffffff, &tmrptr->cpra); |