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authorLinus Torvalds <torvalds@linux-foundation.org>2009-03-30 10:36:35 -0700
committerLinus Torvalds <torvalds@linux-foundation.org>2009-03-30 10:36:35 -0700
commit915db32ddbc967f023fbf7d7f01cca9e05606a9b (patch)
tree1634540805af363e1514d132d9140aa585f9cc9d /arch/mips/kernel/cpu-probe.c
parentebc8eca169be0283d5a7ab54c4411dd59cfb0f27 (diff)
parent91e8a30e90144bcd0fead02dc57976f304c3b3f7 (diff)
Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus
* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: (21 commits) MIPS: Alchemy: PB1200: use SMC91X platform data. MIPS: Alchemy: MIPS hazard workarounds are not required. MIPS: Alchemy: provide cpu feature overrides. MIPS: Alchemy: unify CPU model constants. MIPS: Make a needlessly global symbol static in arch/mips/kernel/smp.c MIPS: Fix global namespace pollution in arch/mips/kernel/smp-up.c MIPS: Malta: make a needlessly global integer variable static MIPS: Use BUG_ON() where possible. MIPS: Convert obsolete irq_desc_t to struct irq_desc MIPS: Enable GENERIC_HARDIRQS_NO__DO_IRQ for all platforms MIPS: EMMA2RH: Set UART mapbase MIPS: EMMA2RH: Use set_irq_chip_and_handler_name MIPS: EMMA2RH: Use handle_edge_irq() handler for GPIO interrupts MIPS: Mark Eins: Fix cascading interrupt dispatcher MIPS: Au1000: convert to using gpiolib MIPS: Stop using <asm-generic/int-l64.h>. MIPS: Cavium: Add -Werror MIPS: Makefile: Add simple make install target. MIPS: Compat: Zero upper 32-bit of offset_high and offset_low. MIPS: __raw_spin_lock() may spin forever on ticket wrap. ...
Diffstat (limited to 'arch/mips/kernel/cpu-probe.c')
-rw-r--r--arch/mips/kernel/cpu-probe.c21
1 files changed, 4 insertions, 17 deletions
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index 1bdbcad3bb7..b13b8eb3059 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -183,13 +183,7 @@ void __init check_wait(void)
case CPU_TX49XX:
cpu_wait = r4k_wait_irqoff;
break;
- case CPU_AU1000:
- case CPU_AU1100:
- case CPU_AU1500:
- case CPU_AU1550:
- case CPU_AU1200:
- case CPU_AU1210:
- case CPU_AU1250:
+ case CPU_ALCHEMY:
cpu_wait = au1k_wait;
break;
case CPU_20KC:
@@ -783,37 +777,30 @@ static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu)
switch (c->processor_id & 0xff00) {
case PRID_IMP_AU1_REV1:
case PRID_IMP_AU1_REV2:
+ c->cputype = CPU_ALCHEMY;
switch ((c->processor_id >> 24) & 0xff) {
case 0:
- c->cputype = CPU_AU1000;
__cpu_name[cpu] = "Au1000";
break;
case 1:
- c->cputype = CPU_AU1500;
__cpu_name[cpu] = "Au1500";
break;
case 2:
- c->cputype = CPU_AU1100;
__cpu_name[cpu] = "Au1100";
break;
case 3:
- c->cputype = CPU_AU1550;
__cpu_name[cpu] = "Au1550";
break;
case 4:
- c->cputype = CPU_AU1200;
__cpu_name[cpu] = "Au1200";
- if ((c->processor_id & 0xff) == 2) {
- c->cputype = CPU_AU1250;
+ if ((c->processor_id & 0xff) == 2)
__cpu_name[cpu] = "Au1250";
- }
break;
case 5:
- c->cputype = CPU_AU1210;
__cpu_name[cpu] = "Au1210";
break;
default:
- panic("Unknown Au Core!");
+ __cpu_name[cpu] = "Au1xxx";
break;
}
break;