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authorKevin D. Kissell <kevink@mips.com>2007-07-27 18:45:25 +0100
committerRalf Baechle <ralf@linux-mips.org>2007-07-31 21:35:24 +0100
commitc3a005f4b6a7752608e75d016ef8d07c55285e48 (patch)
tree90d45d432eff668e751da22640021e3e0c326504 /arch/mips/mips-boards
parentefaa534ed191662270e3be143c8a038a7492ce8f (diff)
[MIPS] SMTC: Safety net for i8259A interrupts.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/mips-boards')
-rw-r--r--arch/mips/mips-boards/malta/malta_int.c12
1 files changed, 12 insertions, 0 deletions
diff --git a/arch/mips/mips-boards/malta/malta_int.c b/arch/mips/mips-boards/malta/malta_int.c
index c78d4834960..97aeb8c4e60 100644
--- a/arch/mips/mips-boards/malta/malta_int.c
+++ b/arch/mips/mips-boards/malta/malta_int.c
@@ -330,6 +330,18 @@ void __init arch_init_irq(void)
(0x100 << MIPSCPU_INT_I8259A));
setup_irq_smtc (MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI,
&corehi_irqaction, (0x100 << MIPSCPU_INT_COREHI));
+ /*
+ * Temporary hack to ensure that the subsidiary device
+ * interrupts coing in via the i8259A, but associated
+ * with low IRQ numbers, will restore the Status.IM
+ * value associated with the i8259A.
+ */
+ {
+ int i;
+
+ for (i = 0; i < 16; i++)
+ irq_hwmask[i] = (0x100 << MIPSCPU_INT_I8259A);
+ }
#else /* Not SMTC */
setup_irq (MIPS_CPU_IRQ_BASE+MIPSCPU_INT_I8259A, &i8259irq);
setup_irq (MIPS_CPU_IRQ_BASE+MIPSCPU_INT_COREHI, &corehi_irqaction);