[MIPS] Complete fixes after removal of pt_regs argument to int handlers.

Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

6 files changed, 44 insertions, 45 deletions

diff --git a/arch/mips/mips-boards/atlas/atlas_int.c b/arch/mips/mips-boards/atlas/atlas_int.c
index a020a3cb4f4..be624b8c3b0 100644
--- a/arch/mips/mips-boards/atlas/atlas_int.c
+++ b/arch/mips/mips-boards/atlas/atlas_int.c
@@ -101,7 +101,7 @@ static inline int ls1bit32(unsigned int x)
 	return b;
 }
 
-static inline void atlas_hw0_irqdispatch(struct pt_regs *regs)
+static inline void atlas_hw0_irqdispatch(void)
 {
 	unsigned long int_status;
 	int irq;
@@ -116,7 +116,7 @@ static inline void atlas_hw0_irqdispatch(struct pt_regs *regs)
 
 	DEBUG_INT("atlas_hw0_irqdispatch: irq=%d\n", irq);
 
-	do_IRQ(irq, regs);
+	do_IRQ(irq);
 }
 
 static inline int clz(unsigned long x)
@@ -188,7 +188,7 @@ static inline unsigned int irq_ffs(unsigned int pending)
  * then we just return, if multiple IRQs are pending then we will just take
  * another exception, big deal.
  */
-asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
+asmlinkage void plat_irq_dispatch(void)
 {
 	unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM;
 	int irq;
@@ -196,11 +196,11 @@ asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
 	irq = irq_ffs(pending);
 
 	if (irq == MIPSCPU_INT_ATLAS)
-		atlas_hw0_irqdispatch(regs);
+		atlas_hw0_irqdispatch();
 	else if (irq >= 0)
-		do_IRQ(MIPSCPU_INT_BASE + irq, regs);
+		do_IRQ(MIPSCPU_INT_BASE + irq);
 	else
-		spurious_interrupt(regs);
+		spurious_interrupt();
 }
 
 static inline void init_atlas_irqs (int base)
diff --git a/arch/mips/mips-boards/generic/time.c b/arch/mips/mips-boards/generic/time.c
index 8d15861fce6..d379000162f 100644
--- a/arch/mips/mips-boards/generic/time.c
+++ b/arch/mips/mips-boards/generic/time.c
@@ -82,19 +82,19 @@ static inline void scroll_display_message(void)
 	}
 }
 
-static void mips_timer_dispatch (struct pt_regs *regs)
+static void mips_timer_dispatch(void)
 {
-	do_IRQ (mips_cpu_timer_irq, regs);
+	do_IRQ(mips_cpu_timer_irq);
 }
 
 /*
  * Redeclare until I get around mopping the timer code insanity on MIPS.
  */
-extern int null_perf_irq(struct pt_regs *regs);
+extern int null_perf_irq(void);
 
-extern int (*perf_irq)(struct pt_regs *regs);
+extern int (*perf_irq)(void);
 
-irqreturn_t mips_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
+irqreturn_t mips_timer_interrupt(int irq, void *dev_id)
 {
 	int cpu = smp_processor_id();
 
@@ -119,7 +119,7 @@ irqreturn_t mips_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
 	 * perf counter overflow, or both.
 	 */
 	if (read_c0_cause() & (1 << 26))
-		perf_irq(regs);
+		perf_irq();
 
 	if (read_c0_cause() & (1 << 30)) {
 		/* If timer interrupt, make it de-assert */
@@ -139,13 +139,13 @@ irqreturn_t mips_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
 		 * the tick on VPE 0 to run the full timer_interrupt().
 		 */
 		if (cpu_data[cpu].vpe_id == 0) {
-				timer_interrupt(irq, NULL, regs);
+				timer_interrupt(irq, NULL);
 				smtc_timer_broadcast(cpu_data[cpu].vpe_id);
 				scroll_display_message();
 		} else {
 			write_c0_compare(read_c0_count() +
 			                 (mips_hpt_frequency/HZ));
-			local_timer_interrupt(irq, dev_id, regs);
+			local_timer_interrupt(irq, dev_id);
 			smtc_timer_broadcast(cpu_data[cpu].vpe_id);
 		}
 	}
@@ -159,12 +159,12 @@ irqreturn_t mips_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
 		 * timer int.
 		 */
 		if (!r2 || (read_c0_cause() & (1 << 26)))
-			if (perf_irq(regs))
+			if (perf_irq())
 				goto out;
 
 		/* we keep interrupt disabled all the time */
 		if (!r2 || (read_c0_cause() & (1 << 30)))
-			timer_interrupt(irq, NULL, regs);
+			timer_interrupt(irq, NULL);
 
 		scroll_display_message();
 	} else {
@@ -180,7 +180,7 @@ irqreturn_t mips_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
 		/*
 		 * Other CPUs should do profiling and process accounting
 		 */
-		local_timer_interrupt(irq, dev_id, regs);
+		local_timer_interrupt(irq, dev_id);
 	}
 out:
 #endif /* CONFIG_MIPS_MT_SMTC */
diff --git a/arch/mips/mips-boards/malta/malta_int.c b/arch/mips/mips-boards/malta/malta_int.c
index 7cc0ba4f553..ed221dc7f6a 100644
--- a/arch/mips/mips-boards/malta/malta_int.c
+++ b/arch/mips/mips-boards/malta/malta_int.c
@@ -114,7 +114,7 @@ static inline int get_int(void)
 	return irq;
 }
 
-static void malta_hw0_irqdispatch(struct pt_regs *regs)
+static void malta_hw0_irqdispatch(void)
 {
 	int irq;
 
@@ -123,17 +123,21 @@ static void malta_hw0_irqdispatch(struct pt_regs *regs)
 		return;  /* interrupt has already been cleared */
 	}
 
-	do_IRQ(MALTA_INT_BASE+irq, regs);
+	do_IRQ(MALTA_INT_BASE + irq);
 }
 
-void corehi_irqdispatch(struct pt_regs *regs)
+static void corehi_irqdispatch(void)
 {
+	unsigned int intedge, intsteer, pcicmd, pcibadaddr;
+        unsigned int pcimstat, intisr, inten, intpol;
 	unsigned int intrcause,datalo,datahi;
-        unsigned int pcimstat, intisr, inten, intpol, intedge, intsteer, pcicmd, pcibadaddr;
+	struct pt_regs *regs;
 
         printk("CoreHI interrupt, shouldn't happen, so we die here!!!\n");
-        printk("epc   : %08lx\nStatus: %08lx\nCause : %08lx\nbadVaddr : %08lx\n"
-, regs->cp0_epc, regs->cp0_status, regs->cp0_cause, regs->cp0_badvaddr);
+        printk("epc   : %08lx\nStatus: %08lx\n"
+	       "Cause : %08lx\nbadVaddr : %08lx\n",
+	       regs->cp0_epc, regs->cp0_status,
+	       regs->cp0_cause, regs->cp0_badvaddr);
 
 	/* Read all the registers and then print them as there is a
 	   problem with interspersed printk's upsetting the Bonito controller.
@@ -146,7 +150,7 @@ void corehi_irqdispatch(struct pt_regs *regs)
         case MIPS_REVISION_CORID_CORE_FPGA3:
         case MIPS_REVISION_CORID_CORE_24K:
         case MIPS_REVISION_CORID_CORE_EMUL_MSC:
-                ll_msc_irq(regs);
+                ll_msc_irq();
                 break;
         case MIPS_REVISION_CORID_QED_RM5261:
         case MIPS_REVISION_CORID_CORE_LV:
@@ -255,7 +259,7 @@ static inline unsigned int irq_ffs(unsigned int pending)
  * another exception, big deal.
  */
 
-asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
+asmlinkage void plat_irq_dispatch(void)
 {
 	unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM;
 	int irq;
@@ -263,11 +267,11 @@ asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
 	irq = irq_ffs(pending);
 
 	if (irq == MIPSCPU_INT_I8259A)
-		malta_hw0_irqdispatch(regs);
+		malta_hw0_irqdispatch();
 	else if (irq > 0)
-		do_IRQ(MIPSCPU_INT_BASE + irq, regs);
+		do_IRQ(MIPSCPU_INT_BASE + irq);
 	else
-		spurious_interrupt(regs);
+		spurious_interrupt();
 }
 
 static struct irqaction i8259irq = {
diff --git a/arch/mips/mips-boards/sead/sead_int.c b/arch/mips/mips-boards/sead/sead_int.c
index 9168d934c66..f445fcddfdf 100644
--- a/arch/mips/mips-boards/sead/sead_int.c
+++ b/arch/mips/mips-boards/sead/sead_int.c
@@ -98,7 +98,7 @@ static inline unsigned int irq_ffs(unsigned int pending)
  * then we just return, if multiple IRQs are pending then we will just take
  * another exception, big deal.
  */
-asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
+asmlinkage void plat_irq_dispatch(void)
 {
 	unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM;
 	int irq;
@@ -106,7 +106,7 @@ asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
 	irq = irq_ffs(pending);
 
 	if (irq >= 0)
-		do_IRQ(MIPSCPU_INT_BASE + irq, regs);
+		do_IRQ(MIPSCPU_INT_BASE + irq);
 	else
 		spurious_interrupt(regs);
 }
diff --git a/arch/mips/mips-boards/sim/sim_int.c b/arch/mips/mips-boards/sim/sim_int.c
index 2c15c8efec4..2ce449dce6f 100644
--- a/arch/mips/mips-boards/sim/sim_int.c
+++ b/arch/mips/mips-boards/sim/sim_int.c
@@ -71,12 +71,7 @@ static inline unsigned int irq_ffs(unsigned int pending)
 #endif
 }
 
-static inline void sim_hw0_irqdispatch(struct pt_regs *regs)
-{
-	do_IRQ(2, regs);
-}
-
-asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
+asmlinkage void plat_irq_dispatch(void)
 {
 	unsigned int pending = read_c0_cause() & read_c0_status() & ST0_IM;
 	int irq;
@@ -84,9 +79,9 @@ asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
 	irq = irq_ffs(pending);
 
 	if (irq > 0)
-		do_IRQ(MIPSCPU_INT_BASE + irq, regs);
+		do_IRQ(MIPSCPU_INT_BASE + irq);
 	else
-		spurious_interrupt(regs);
+		spurious_interrupt();
 }
 
 void __init arch_init_irq(void)
diff --git a/arch/mips/mips-boards/sim/sim_time.c b/arch/mips/mips-boards/sim/sim_time.c
index 230929ecd57..acd83a37955 100644
--- a/arch/mips/mips-boards/sim/sim_time.c
+++ b/arch/mips/mips-boards/sim/sim_time.c
@@ -33,7 +33,7 @@
 
 unsigned long cpu_khz;
 
-irqreturn_t sim_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
+irqreturn_t sim_timer_interrupt(int irq, void *dev_id)
 {
 #ifdef CONFIG_SMP
 	int cpu = smp_processor_id();
@@ -44,7 +44,7 @@ irqreturn_t sim_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
 	 */
 #ifndef CONFIG_MIPS_MT_SMTC
 	if (cpu == 0) {
-		timer_interrupt(irq, dev_id, regs);
+		timer_interrupt(irq, dev_id);
 	}
 	else {
 		/* Everyone else needs to reset the timer int here as
@@ -84,7 +84,7 @@ irqreturn_t sim_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
 	irq_enable_hazard();
 	evpe(vpflags);
 
-	if(cpu_data[cpu].vpe_id == 0) timer_interrupt(irq, dev_id, regs);
+	if(cpu_data[cpu].vpe_id == 0) timer_interrupt(irq, dev_id);
 	else write_c0_compare (read_c0_count() + ( mips_hpt_frequency/HZ));
 	smtc_timer_broadcast(cpu_data[cpu].vpe_id);
 
@@ -93,10 +93,10 @@ irqreturn_t sim_timer_interrupt(int irq, void *dev_id, struct pt_regs *regs)
 	/*
 	 * every CPU should do profiling and process accounting
 	 */
- 	local_timer_interrupt (irq, dev_id, regs);
+ 	local_timer_interrupt (irq, dev_id);
 	return IRQ_HANDLED;
 #else
-	return timer_interrupt (irq, dev_id, regs);
+	return timer_interrupt (irq, dev_id);
 #endif
 }
 
@@ -177,9 +177,9 @@ void __init sim_time_init(void)
 
 static int mips_cpu_timer_irq;
 
-static void mips_timer_dispatch (struct pt_regs *regs)
+static void mips_timer_dispatch(void)
 {
-	do_IRQ (mips_cpu_timer_irq, regs);
+	do_IRQ(mips_cpu_timer_irq);
 }