Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus

* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: (21 commits)
  MIPS: Alchemy: PB1200: use SMC91X platform data.
  MIPS: Alchemy: MIPS hazard workarounds are not required.
  MIPS: Alchemy: provide cpu feature overrides.
  MIPS: Alchemy: unify CPU model constants.
  MIPS: Make a needlessly global symbol static in arch/mips/kernel/smp.c
  MIPS: Fix global namespace pollution in arch/mips/kernel/smp-up.c
  MIPS: Malta: make a needlessly global integer variable static
  MIPS: Use BUG_ON() where possible.
  MIPS: Convert obsolete irq_desc_t to struct irq_desc
  MIPS: Enable GENERIC_HARDIRQS_NO__DO_IRQ for all platforms
  MIPS: EMMA2RH: Set UART mapbase
  MIPS: EMMA2RH: Use set_irq_chip_and_handler_name
  MIPS: EMMA2RH: Use handle_edge_irq() handler for GPIO interrupts
  MIPS: Mark Eins: Fix cascading interrupt dispatcher
  MIPS: Au1000: convert to using gpiolib
  MIPS: Stop using <asm-generic/int-l64.h>.
  MIPS: Cavium: Add -Werror
  MIPS: Makefile: Add simple make install target.
  MIPS: Compat: Zero upper 32-bit of offset_high and offset_low.
  MIPS: __raw_spin_lock() may spin forever on ticket wrap.
  ...

1 files changed, 5 insertions, 12 deletions

diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c
index 871e828bc62..58d9075e86f 100644
--- a/arch/mips/mm/c-r4k.c
+++ b/arch/mips/mm/c-r4k.c
@@ -1026,13 +1026,7 @@ static void __cpuinit probe_pcache(void)
 		c->icache.flags |= MIPS_CACHE_VTAG;
 		break;
 
-	case CPU_AU1000:
-	case CPU_AU1500:
-	case CPU_AU1100:
-	case CPU_AU1550:
-	case CPU_AU1200:
-	case CPU_AU1210:
-	case CPU_AU1250:
+	case CPU_ALCHEMY:
 		c->icache.flags |= MIPS_CACHE_IC_F_DC;
 		break;
 	}
@@ -1244,7 +1238,7 @@ void au1x00_fixup_config_od(void)
 	/*
 	 * Au1100 errata actually keeps silence about this bit, so we set it
 	 * just in case for those revisions that require it to be set according
-	 * to arch/mips/au1000/common/cputable.c
+	 * to the (now gone) cpu table.
 	 */
 	case 0x02030200: /* Au1100 AB */
 	case 0x02030201: /* Au1100 BA */
@@ -1314,11 +1308,10 @@ static void __cpuinit coherency_setup(void)
 		break;
 	/*
 	 * We need to catch the early Alchemy SOCs with
-	 * the write-only co_config.od bit and set it back to one...
+	 * the write-only co_config.od bit and set it back to one on:
+	 * Au1000 rev DA, HA, HB;  Au1100 AB, BA, BC, Au1500 AB
 	 */
-	case CPU_AU1000: /* rev. DA, HA, HB */
-	case CPU_AU1100: /* rev. AB, BA, BC ?? */
-	case CPU_AU1500: /* rev. AB */
+	case CPU_ALCHEMY:
 		au1x00_fixup_config_od();
 		break;