aboutsummaryrefslogtreecommitdiff
path: root/arch/mips/momentum/ocelot_c
diff options
context:
space:
mode:
authorRalf Baechle <ralf@linux-mips.org>2006-04-03 17:56:36 +0100
committerRalf Baechle <ralf@linux-mips.org>2006-04-19 04:14:21 +0200
commite4ac58afdfac792c0583af30dbd9eae53e24c78b (patch)
tree7517bef2c515fc630e4d3d238867b91cde96f558 /arch/mips/momentum/ocelot_c
parentd35d473c25d43d7db3e5e18b66d558d2a631cca8 (diff)
[MIPS] Rewrite all the assembler interrupt handlers to C.
Saves like 1,600 lines of code, is way easier to debug, compilers frequently do a better job than the cut and paste type of handlers many boards had. And finally having all the stuff done in a single place also means alot of bug potencial for the MT ASE is gone. The only surviving handler in assembler is the DECstation one; I hope Maciej will rewrite it. Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch/mips/momentum/ocelot_c')
-rw-r--r--arch/mips/momentum/ocelot_c/Makefile2
-rw-r--r--arch/mips/momentum/ocelot_c/int-handler.S103
-rw-r--r--arch/mips/momentum/ocelot_c/irq.c30
3 files changed, 28 insertions, 107 deletions
diff --git a/arch/mips/momentum/ocelot_c/Makefile b/arch/mips/momentum/ocelot_c/Makefile
index 91240777f97..94802b4db47 100644
--- a/arch/mips/momentum/ocelot_c/Makefile
+++ b/arch/mips/momentum/ocelot_c/Makefile
@@ -2,7 +2,7 @@
# Makefile for Momentum Computer's Ocelot-C and -CS boards.
#
-obj-y += cpci-irq.o int-handler.o irq.o prom.o reset.o \
+obj-y += cpci-irq.o irq.o prom.o reset.o \
setup.o uart-irq.o
obj-$(CONFIG_KGDB) += dbg_io.o
diff --git a/arch/mips/momentum/ocelot_c/int-handler.S b/arch/mips/momentum/ocelot_c/int-handler.S
deleted file mode 100644
index f77834193c3..00000000000
--- a/arch/mips/momentum/ocelot_c/int-handler.S
+++ /dev/null
@@ -1,103 +0,0 @@
-/*
- * Copyright 2002 Momentum Computer Inc.
- * Author: Matthew Dharm <mdharm@momenco.com>
- *
- * Copyright 2001 MontaVista Software Inc.
- * Author: jsun@mvista.com or jsun@junsun.net
- *
- * First-level interrupt dispatcher for Ocelot-CS board.
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the
- * Free Software Foundation; either version 2 of the License, or (at your
- * option) any later version.
- */
-#include <asm/asm.h>
-#include <asm/mipsregs.h>
-#include <asm/addrspace.h>
-#include <asm/regdef.h>
-#include <asm/stackframe.h>
-#include "ocelot_c_fpga.h"
-
-/*
- * First level interrupt dispatcher for Ocelot-CS board
- */
- .align 5
- NESTED(ocelot_handle_int, PT_SIZE, sp)
- SAVE_ALL
- CLI
- .set at
- mfc0 t0, CP0_CAUSE
- mfc0 t2, CP0_STATUS
-
- and t0, t2
-
- andi t1, t0, STATUSF_IP0 /* sw0 software interrupt */
- bnez t1, ll_sw0_irq
- andi t1, t0, STATUSF_IP1 /* sw1 software interrupt */
- bnez t1, ll_sw1_irq
- andi t1, t0, STATUSF_IP2 /* int0 hardware line */
- bnez t1, ll_scsi_irq
- andi t1, t0, STATUSF_IP3 /* int1 hardware line */
- bnez t1, ll_uart_decode_irq
- andi t1, t0, STATUSF_IP4 /* int2 hardware line */
- bnez t1, ll_pmc_irq
- andi t1, t0, STATUSF_IP5 /* int3 hardware line */
- bnez t1, ll_cpci_decode_irq
- andi t1, t0, STATUSF_IP6 /* int4 hardware line */
- bnez t1, ll_mv64340_decode_irq
- andi t1, t0, STATUSF_IP7 /* cpu timer */
- bnez t1, ll_cputimer_irq
-
- .set reorder
-
- /* wrong alarm or masked ... */
- jal spurious_interrupt
- nop
- j ret_from_irq
- END(ocelot_handle_int)
-
- .align 5
-ll_sw0_irq:
- li a0, 0
- move a1, sp
- jal do_IRQ
- j ret_from_irq
-ll_sw1_irq:
- li a0, 1
- move a1, sp
- jal do_IRQ
- j ret_from_irq
-ll_scsi_irq:
- li a0, 2
- move a1, sp
- jal do_IRQ
- j ret_from_irq
-
-ll_uart_decode_irq:
- move a0, sp
- jal ll_uart_irq
- j ret_from_irq
-
-ll_pmc_irq:
- li a0, 4
- move a1, sp
- jal do_IRQ
- j ret_from_irq
-
-ll_cpci_decode_irq:
- move a0, sp
- jal ll_cpci_irq
- j ret_from_irq
-
-ll_mv64340_decode_irq:
- move a0, sp
- jal ll_mv64340_irq
- j ret_from_irq
-
-ll_cputimer_irq:
- li a0, 7
- move a1, sp
- jal do_IRQ
- j ret_from_irq
-
diff --git a/arch/mips/momentum/ocelot_c/irq.c b/arch/mips/momentum/ocelot_c/irq.c
index a5764bc20e3..86f61ce59e5 100644
--- a/arch/mips/momentum/ocelot_c/irq.c
+++ b/arch/mips/momentum/ocelot_c/irq.c
@@ -48,7 +48,6 @@
#include <asm/mipsregs.h>
#include <asm/system.h>
-extern asmlinkage void ocelot_handle_int(void);
extern void uart_irq_init(void);
extern void cpci_irq_init(void);
@@ -60,6 +59,33 @@ static struct irqaction cascade_mv64340 = {
no_action, SA_INTERRUPT, CPU_MASK_NONE, "cascade via MV64340", NULL, NULL
};
+extern void ll_uart_irq(struct pt_regs *regs);
+extern void ll_cpci_irq(struct pt_regs *regs);
+
+asmlinkage void plat_irq_dispatch(struct pt_regs *regs)
+{
+ unsigned int pending = read_c0_cause() & read_c0_status();
+
+ if (pending & STATUSF_IP0)
+ do_IRQ(0, regs);
+ else if (pending & STATUSF_IP1)
+ do_IRQ(1, regs);
+ else if (pending & STATUSF_IP2)
+ do_IRQ(2, regs);
+ else if (pending & STATUSF_IP3)
+ ll_uart_irq(regs);
+ else if (pending & STATUSF_IP4)
+ do_IRQ(4, regs);
+ else if (pending & STATUSF_IP5)
+ ll_cpci_irq(regs);
+ else if (pending & STATUSF_IP6)
+ ll_mv64340_irq(regs);
+ else if (pending & STATUSF_IP7)
+ do_IRQ(7, regs);
+ else
+ spurious_interrupt(regs);
+}
+
void __init arch_init_irq(void)
{
/*
@@ -68,8 +94,6 @@ void __init arch_init_irq(void)
*/
clear_c0_status(ST0_IM);
- /* Sets the first-level interrupt dispatcher. */
- set_except_vector(0, ocelot_handle_int);
mips_cpu_irq_init(0);
/* set up the cascading interrupts */