aboutsummaryrefslogtreecommitdiff
path: root/arch/mips/sibyte/bcm1480/irq.c
diff options
context:
space:
mode:
authorLinus Torvalds <torvalds@woody.linux-foundation.org>2007-09-10 14:43:37 -0700
committerLinus Torvalds <torvalds@woody.linux-foundation.org>2007-09-10 14:43:37 -0700
commit897ee77bfba12b83752027427a41009961458ee6 (patch)
tree2caf21fd61ab29d5e5ac37e45ff70b55ceeff9c9 /arch/mips/sibyte/bcm1480/irq.c
parentf3f94ce5dba6e134cf0958dd3a42ab28a028fc83 (diff)
parent43863074659b71345b0047c2cf2ff8d8f7a4b4a1 (diff)
Merge branch 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus
* 'upstream' of git://ftp.linux-mips.org/pub/scm/upstream-linus: [MIPS] Ocelot: remove remaining bits [MIPS] TLB: Fix instruction bitmasks [MIPS] R10000: Fix wrong test in dma-default.c [MIPS] Provide empty irq_enable_hazard definition for legacy and R1 cores. [MIPS] Sibyte: Remove broken dependency on EXPERIMENTAL from SIBYTE_SB1xxx_SOC. [MIPS] Kconfig: whitespace cleanup. [MIPS] PCI: Set need_domain_info if controller domain index is non-zero. [MIPS] BCM1480: Fix computation of interrupt mask address register. [MIPS] i8259: Add disable method. [MIPS] tty: add the new ioctls and definitions.
Diffstat (limited to 'arch/mips/sibyte/bcm1480/irq.c')
-rw-r--r--arch/mips/sibyte/bcm1480/irq.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/arch/mips/sibyte/bcm1480/irq.c b/arch/mips/sibyte/bcm1480/irq.c
index 79ae6ef979b..e729b5f3026 100644
--- a/arch/mips/sibyte/bcm1480/irq.c
+++ b/arch/mips/sibyte/bcm1480/irq.c
@@ -100,8 +100,8 @@ DEFINE_SPINLOCK(bcm1480_imr_lock);
void bcm1480_mask_irq(int cpu, int irq)
{
- unsigned long flags;
- u64 cur_ints,hl_spacing;
+ unsigned long flags, hl_spacing;
+ u64 cur_ints;
spin_lock_irqsave(&bcm1480_imr_lock, flags);
hl_spacing = 0;
@@ -117,8 +117,8 @@ void bcm1480_mask_irq(int cpu, int irq)
void bcm1480_unmask_irq(int cpu, int irq)
{
- unsigned long flags;
- u64 cur_ints,hl_spacing;
+ unsigned long flags, hl_spacing;
+ u64 cur_ints;
spin_lock_irqsave(&bcm1480_imr_lock, flags);
hl_spacing = 0;