diff options
| author | Josh Boyer <jwboyer@linux.vnet.ibm.com> | 2008-06-18 08:34:39 +1000 |
|---|---|---|
| committer | Paul Mackerras <paulus@samba.org> | 2008-06-18 21:40:43 +1000 |
| commit | b17879f71c2eb4a10f5a63918819d9d572b23a9a (patch) | |
| tree | 9a23e42f6d0aedaa2e8049d0338650a10934903b /arch/mips | |
| parent | 952f4a0a9b27e6dbd5d32e330b3f609ebfa0b061 (diff) | |
[POWERPC] 4xx: Clear new TLB cache attribute bits in Data Storage vector
A recent commit added support for the new 440x6 and 464 cores that have the
added WL1, IL1I, IL1D, IL2I, and ILD2 bits for the caching attributes in the
TLBs. The new bits were cleared in the finish_tlb_load function, however a
similar bit of code was missed in the DataStorage interrupt vector.
Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat (limited to 'arch/mips')
0 files changed, 0 insertions, 0 deletions