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authorKyle McMartin <kyle@mcmartin.ca>2008-07-28 23:02:13 -0400
committerKyle McMartin <kyle@hera.kernel.org>2008-10-10 16:32:29 +0000
commitdeae26bf6a10e47983606f5df080b91e97650ead (patch)
tree84a8a68145d0f713d7c5a1f9e6b3b03be9b3a4c8 /arch/parisc/include/asm/prefetch.h
parent6c86cb8237bf08443806089130dc108051569a93 (diff)
parisc: move include/asm-parisc to arch/parisc/include/asm
Diffstat (limited to 'arch/parisc/include/asm/prefetch.h')
-rw-r--r--arch/parisc/include/asm/prefetch.h39
1 files changed, 39 insertions, 0 deletions
diff --git a/arch/parisc/include/asm/prefetch.h b/arch/parisc/include/asm/prefetch.h
new file mode 100644
index 00000000000..c5edc60c059
--- /dev/null
+++ b/arch/parisc/include/asm/prefetch.h
@@ -0,0 +1,39 @@
+/*
+ * include/asm-parisc/prefetch.h
+ *
+ * PA 2.0 defines data prefetch instructions on page 6-11 of the Kane book.
+ * In addition, many implementations do hardware prefetching of both
+ * instructions and data.
+ *
+ * PA7300LC (page 14-4 of the ERS) also implements prefetching by a load
+ * to gr0 but not in a way that Linux can use. If the load would cause an
+ * interruption (eg due to prefetching 0), it is suppressed on PA2.0
+ * processors, but not on 7300LC.
+ *
+ */
+
+#ifndef __ASM_PARISC_PREFETCH_H
+#define __ASM_PARISC_PREFETCH_H
+
+#ifndef __ASSEMBLY__
+#ifdef CONFIG_PREFETCH
+
+#define ARCH_HAS_PREFETCH
+static inline void prefetch(const void *addr)
+{
+ __asm__("ldw 0(%0), %%r0" : : "r" (addr));
+}
+
+/* LDD is a PA2.0 addition. */
+#ifdef CONFIG_PA20
+#define ARCH_HAS_PREFETCHW
+static inline void prefetchw(const void *addr)
+{
+ __asm__("ldd 0(%0), %%r0" : : "r" (addr));
+}
+#endif /* CONFIG_PA20 */
+
+#endif /* CONFIG_PREFETCH */
+#endif /* __ASSEMBLY__ */
+
+#endif /* __ASM_PARISC_PROCESSOR_H */