aboutsummaryrefslogtreecommitdiff
path: root/arch/powerpc/boot/dts/mpc8555cds.dts
diff options
context:
space:
mode:
authorAndy Fleming <afleming@freescale.com>2006-08-18 18:04:34 -0500
committerPaul Mackerras <paulus@samba.org>2006-08-23 15:51:18 +1000
commit2654d6385f6cad00cfb8f5087aeb10d0ed781e74 (patch)
treea9aebfe0e043a90bc0f537e93453154a3e3cd435 /arch/powerpc/boot/dts/mpc8555cds.dts
parentddd64159eb0d090766eee79b191a974ffdd83a42 (diff)
[POWERPC] Add 85xx DTS files to powerpc
Added the mpc85xx family of dts files to the powerpc tree Signed-off-by: Paul Mackerras <paulus@samba.org>
Diffstat (limited to 'arch/powerpc/boot/dts/mpc8555cds.dts')
-rw-r--r--arch/powerpc/boot/dts/mpc8555cds.dts244
1 files changed, 244 insertions, 0 deletions
diff --git a/arch/powerpc/boot/dts/mpc8555cds.dts b/arch/powerpc/boot/dts/mpc8555cds.dts
new file mode 100644
index 00000000000..118f5a88765
--- /dev/null
+++ b/arch/powerpc/boot/dts/mpc8555cds.dts
@@ -0,0 +1,244 @@
+/*
+ * MPC8555 CDS Device Tree Source
+ *
+ * Copyright 2006 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify it
+ * under the terms of the GNU General Public License as published by the
+ * Free Software Foundation; either version 2 of the License, or (at your
+ * option) any later version.
+ */
+
+
+/ {
+ model = "MPC8555CDS";
+ compatible = "MPC85xxCDS";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ linux,phandle = <100>;
+
+ cpus {
+ #cpus = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ linux,phandle = <200>;
+
+ PowerPC,8555@0 {
+ device_type = "cpu";
+ reg = <0>;
+ d-cache-line-size = <20>; // 32 bytes
+ i-cache-line-size = <20>; // 32 bytes
+ d-cache-size = <8000>; // L1, 32K
+ i-cache-size = <8000>; // L1, 32K
+ timebase-frequency = <0>; // 33 MHz, from uboot
+ bus-frequency = <0>; // 166 MHz
+ clock-frequency = <0>; // 825 MHz, from uboot
+ 32-bit;
+ linux,phandle = <201>;
+ };
+ };
+
+ memory {
+ device_type = "memory";
+ linux,phandle = <300>;
+ reg = <00000000 08000000>; // 128M at 0x0
+ };
+
+ soc8555@e0000000 {
+ #address-cells = <1>;
+ #size-cells = <1>;
+ #interrupt-cells = <2>;
+ device_type = "soc";
+ ranges = <0 e0000000 00100000>;
+ reg = <e0000000 00100000>; // CCSRBAR 1M
+ bus-frequency = <0>;
+
+ i2c@3000 {
+ device_type = "i2c";
+ compatible = "fsl-i2c";
+ reg = <3000 100>;
+ interrupts = <1b 2>;
+ interrupt-parent = <40000>;
+ dfsrr;
+ };
+
+ mdio@24520 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ device_type = "mdio";
+ compatible = "gianfar";
+ reg = <24520 20>;
+ linux,phandle = <24520>;
+ ethernet-phy@0 {
+ linux,phandle = <2452000>;
+ interrupt-parent = <40000>;
+ interrupts = <35 0>;
+ reg = <0>;
+ device_type = "ethernet-phy";
+ };
+ ethernet-phy@1 {
+ linux,phandle = <2452001>;
+ interrupt-parent = <40000>;
+ interrupts = <35 0>;
+ reg = <1>;
+ device_type = "ethernet-phy";
+ };
+ };
+
+ ethernet@24000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ device_type = "network";
+ model = "TSEC";
+ compatible = "gianfar";
+ reg = <24000 1000>;
+ local-mac-address = [ 00 E0 0C 00 73 00 ];
+ interrupts = <0d 2 0e 2 12 2>;
+ interrupt-parent = <40000>;
+ phy-handle = <2452000>;
+ };
+
+ ethernet@25000 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ device_type = "network";
+ model = "TSEC";
+ compatible = "gianfar";
+ reg = <25000 1000>;
+ local-mac-address = [ 00 E0 0C 00 73 01 ];
+ interrupts = <13 2 14 2 18 2>;
+ interrupt-parent = <40000>;
+ phy-handle = <2452001>;
+ };
+
+ serial@4500 {
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <4500 100>; // reg base, size
+ clock-frequency = <0>; // should we fill in in uboot?
+ interrupts = <1a 2>;
+ interrupt-parent = <40000>;
+ };
+
+ serial@4600 {
+ device_type = "serial";
+ compatible = "ns16550";
+ reg = <4600 100>; // reg base, size
+ clock-frequency = <0>; // should we fill in in uboot?
+ interrupts = <1a 2>;
+ interrupt-parent = <40000>;
+ };
+
+ pci@8000 {
+ linux,phandle = <8000>;
+ interrupt-map-mask = <1f800 0 0 7>;
+ interrupt-map = <
+
+ /* IDSEL 0x10 */
+ 08000 0 0 1 40000 30 1
+ 08000 0 0 2 40000 31 1
+ 08000 0 0 3 40000 32 1
+ 08000 0 0 4 40000 33 1
+
+ /* IDSEL 0x11 */
+ 08800 0 0 1 40000 30 1
+ 08800 0 0 2 40000 31 1
+ 08800 0 0 3 40000 32 1
+ 08800 0 0 4 40000 33 1
+
+ /* IDSEL 0x12 (Slot 1) */
+ 09000 0 0 1 40000 30 1
+ 09000 0 0 2 40000 31 1
+ 09000 0 0 3 40000 32 1
+ 09000 0 0 4 40000 33 1
+
+ /* IDSEL 0x13 (Slot 2) */
+ 09800 0 0 1 40000 31 1
+ 09800 0 0 2 40000 32 1
+ 09800 0 0 3 40000 33 1
+ 09800 0 0 4 40000 30 1
+
+ /* IDSEL 0x14 (Slot 3) */
+ 0a000 0 0 1 40000 32 1
+ 0a000 0 0 2 40000 33 1
+ 0a000 0 0 3 40000 30 1
+ 0a000 0 0 4 40000 31 1
+
+ /* IDSEL 0x15 (Slot 4) */
+ 0a800 0 0 1 40000 33 1
+ 0a800 0 0 2 40000 30 1
+ 0a800 0 0 3 40000 31 1
+ 0a800 0 0 4 40000 32 1
+
+ /* Bus 1 (Tundra Bridge) */
+ /* IDSEL 0x12 (ISA bridge) */
+ 19000 0 0 1 40000 30 1
+ 19000 0 0 2 40000 31 1
+ 19000 0 0 3 40000 32 1
+ 19000 0 0 4 40000 33 1>;
+ interrupt-parent = <40000>;
+ interrupts = <08 2>;
+ bus-range = <0 0>;
+ ranges = <02000000 0 80000000 80000000 0 20000000
+ 01000000 0 00000000 e2000000 0 00100000>;
+ clock-frequency = <3f940aa>;
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <8000 1000>;
+ compatible = "85xx";
+ device_type = "pci";
+
+ i8259@19000 {
+ clock-frequency = <0>;
+ interrupt-controller;
+ device_type = "interrupt-controller";
+ reg = <19000 0 0 0 1>;
+ #address-cells = <0>;
+ #interrupt-cells = <2>;
+ built-in;
+ compatible = "chrp,iic";
+ big-endian;
+ interrupts = <1>;
+ interrupt-parent = <8000>;
+ };
+ };
+
+ pci@9000 {
+ linux,phandle = <9000>;
+ interrupt-map-mask = <f800 0 0 7>;
+ interrupt-map = <
+
+ /* IDSEL 0x15 */
+ a800 0 0 1 40000 3b 1
+ a800 0 0 2 40000 3b 1
+ a800 0 0 3 40000 3b 1
+ a800 0 0 4 40000 3b 1>;
+ interrupt-parent = <40000>;
+ interrupts = <09 2>;
+ bus-range = <0 0>;
+ ranges = <02000000 0 a0000000 a0000000 0 20000000
+ 01000000 0 00000000 e3000000 0 00100000>;
+ clock-frequency = <3f940aa>;
+ #interrupt-cells = <1>;
+ #size-cells = <2>;
+ #address-cells = <3>;
+ reg = <9000 1000>;
+ compatible = "85xx";
+ device_type = "pci";
+ };
+
+ pic@40000 {
+ linux,phandle = <40000>;
+ clock-frequency = <0>;
+ interrupt-controller;
+ #address-cells = <0>;
+ #interrupt-cells = <2>;
+ reg = <40000 40000>;
+ built-in;
+ compatible = "chrp,open-pic";
+ device_type = "open-pic";
+ big-endian;
+ };
+ };
+};