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authorPeter Korsgaard <jacmet@sunsite.dk>2009-06-09 13:43:32 +0200
committerKumar Gala <galak@kernel.crashing.org>2009-06-15 21:45:31 -0500
commitb7d66c88c968379ebe683a28c4005895497ebbad (patch)
tree58997c1d300f4f90c1b63479aec9dd8c1f55c054 /arch/powerpc/boot/dts/sbc8349.dts
parent4dc2a6cf82746c1e632aad0cd38615a35f8df075 (diff)
powerpc/mpc83xx: Fix usb mux setup for mpc834x
usb0 and usb1 mux settings in the sicrl register were swapped (twice!) in mpc834x_usb_cfg(), leading to various strange issues with fsl-ehci and full speed devices. The USB port config on mpc834x is done using 2 muxes: Port 0 is always used for MPH port 0, and port 1 can either be used for MPH port 1 or DR (unless DR uses UTMI phy or OTG, then it uses both ports) - See 8349 RM figure 1-4.. mpc8349_usb_cfg() had this inverted for the DR, and it also had the bit positions of the usb0 / usb1 mux settings swapped. It would basically work if you specified port1 instead of port0 for the MPH controller (and happened to use ULPI phys), which is what all the 834x dts have done, even though that configuration is physically invalid. Instead fix mpc8349_usb_cfg() and adjust the dts files to match reality. Signed-off-by: Peter Korsgaard <jacmet@sunsite.dk> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
Diffstat (limited to 'arch/powerpc/boot/dts/sbc8349.dts')
-rw-r--r--arch/powerpc/boot/dts/sbc8349.dts2
1 files changed, 1 insertions, 1 deletions
diff --git a/arch/powerpc/boot/dts/sbc8349.dts b/arch/powerpc/boot/dts/sbc8349.dts
index 5fb6f6684b0..2d9fa68f641 100644
--- a/arch/powerpc/boot/dts/sbc8349.dts
+++ b/arch/powerpc/boot/dts/sbc8349.dts
@@ -144,7 +144,7 @@
interrupt-parent = <&ipic>;
interrupts = <39 0x8>;
phy_type = "ulpi";
- port1;
+ port0;
};
/* phy type (ULPI, UTMI, UTMI_WIDE, SERIAL) */
usb@23000 {