POWERPC: Add support for the mpc8560 eval board

This makes the 8560 evaluation board fully supported under arch/powerpc,
as the first board with CPM2 SoC peripherals. The brand new devicetree
nodes are introduced (intending to be a subset of the QuiccEngine-equipped
models, with dts sources placed into the kernel according to the new convention.

Assuming all the preceding stuff applied (PAL+fs_enet related+ CPM_UART
update), the both TSEC eth ,FCC Eths, and both SCC UARTs are
working. The relevant drivers are still capable to drive users in ppc,
which was verified with 8272ADS (SCC uart+FCC eth).

This is also verified on mpc8540 and actually make it work (PCI stuff
working as well)

Signed-off-by: Vitaly Bordug <vbordug@ru.mvista.com>

1 files changed, 302 insertions, 0 deletions

diff --git a/arch/powerpc/boot/dts/mpc8560ads.dts b/arch/powerpc/boot/dts/mpc8560ads.dts
new file mode 100644
index 00000000000..ba5c943a6fe
--- /dev/null
+++ b/arch/powerpc/boot/dts/mpc8560ads.dts
@@ -0,0 +1,302 @@
+/*
+ * MPC8560 ADS Device Tree Source
+ *
+ * Copyright 2006 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+
+/ {
+	model = "MPC8560ADS";
+	compatible = "MPC85xxADS";
+	#address-cells = <1>;
+	#size-cells = <1>;
+	linux,phandle = <100>;
+
+	cpus {
+		#cpus = <1>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		linux,phandle = <200>;
+
+		PowerPC,8560@0 {
+			device_type = "cpu";
+			reg = <0>;
+			d-cache-line-size = <20>;	// 32 bytes
+			i-cache-line-size = <20>;	// 32 bytes
+			d-cache-size = <8000>;		// L1, 32K
+			i-cache-size = <8000>;		// L1, 32K
+			timebase-frequency = <04ead9a0>;
+			bus-frequency = <13ab6680>;
+			clock-frequency = <312c8040>;
+			32-bit;
+			linux,phandle = <201>;
+			linux,boot-cpu;
+		};
+	};
+
+	memory {
+		device_type = "memory";
+		linux,phandle = <300>;
+		reg = <00000000 10000000>;
+	};
+
+	soc8560@e0000000 {
+		#address-cells = <1>;
+		#size-cells = <1>;
+		#interrupt-cells = <2>;
+		device_type = "soc";
+		ranges = <0 e0000000 00100000>;
+		reg = <e0000000 00000200>;
+		bus-frequency = <13ab6680>;
+
+		mdio@24520 {
+			device_type = "mdio";
+			compatible = "gianfar";
+			reg = <24520 20>;
+			linux,phandle = <24520>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			ethernet-phy@0 {
+				linux,phandle = <2452000>;
+				interrupt-parent = <40000>;
+				interrupts = <35 1>;
+				reg = <0>;
+				device_type = "ethernet-phy";
+			};
+			ethernet-phy@1 {
+				linux,phandle = <2452001>;
+				interrupt-parent = <40000>;
+				interrupts = <35 1>;
+				reg = <1>;
+				device_type = "ethernet-phy";
+			};
+			ethernet-phy@2 {
+				linux,phandle = <2452002>;
+				interrupt-parent = <40000>;
+				interrupts = <37 1>;
+				reg = <2>;
+				device_type = "ethernet-phy";
+			};
+			ethernet-phy@3 {
+				linux,phandle = <2452003>;
+				interrupt-parent = <40000>;
+				interrupts = <37 1>;
+				reg = <3>;
+				device_type = "ethernet-phy";
+			};
+		};
+
+		ethernet@24000 {
+			device_type = "network";
+			model = "TSEC";
+			compatible = "gianfar";
+			reg = <24000 1000>;
+			address = [ 00 00 0C 00 00 FD ];
+			interrupts = <d 2 e 2 12 2>;
+			interrupt-parent = <40000>;
+			phy-handle = <2452000>;
+		};
+
+		ethernet@25000 {
+			#address-cells = <1>;
+			#size-cells = <0>;
+			device_type = "network";
+			model = "TSEC";
+			compatible = "gianfar";
+			reg = <25000 1000>;
+			address = [ 00 00 0C 00 01 FD ];
+			interrupts = <13 2 14 2 18 2>;
+			interrupt-parent = <40000>;
+			phy-handle = <2452001>;
+		};
+
+		pci@8000 {
+			linux,phandle = <8000>;
+			#interrupt-cells = <1>;
+			#size-cells = <2>;
+			#address-cells = <3>;
+			compatible = "85xx";
+			device_type = "pci";
+			reg = <8000 400>;
+			clock-frequency = <3f940aa>;
+			interrupt-map-mask = <f800 0 0 7>;
+			interrupt-map = <
+
+					/* IDSEL 0x2 */
+					 1000 0 0 1 40000 31 1
+					 1000 0 0 2 40000 32 1
+					 1000 0 0 3 40000 33 1
+					 1000 0 0 4 40000 34 1
+
+					/* IDSEL 0x3 */
+					 1800 0 0 1 40000 34 1
+					 1800 0 0 2 40000 31 1
+					 1800 0 0 3 40000 32 1
+					 1800 0 0 4 40000 33 1
+
+					/* IDSEL 0x4 */
+					 2000 0 0 1 40000 33 1
+					 2000 0 0 2 40000 34 1
+					 2000 0 0 3 40000 31 1
+					 2000 0 0 4 40000 32 1
+
+					/* IDSEL 0x5  */
+					 2800 0 0 1 40000 32 1
+					 2800 0 0 2 40000 33 1
+					 2800 0 0 3 40000 34 1
+					 2800 0 0 4 40000 31 1
+
+					/* IDSEL 12 */
+					 6000 0 0 1 40000 31 1
+					 6000 0 0 2 40000 32 1
+					 6000 0 0 3 40000 33 1
+					 6000 0 0 4 40000 34 1
+
+					/* IDSEL 13 */
+					 6800 0 0 1 40000 34 1
+					 6800 0 0 2 40000 31 1
+					 6800 0 0 3 40000 32 1
+					 6800 0 0 4 40000 33 1
+
+					/* IDSEL 14*/
+					 7000 0 0 1 40000 33 1
+					 7000 0 0 2 40000 34 1
+					 7000 0 0 3 40000 31 1
+					 7000 0 0 4 40000 32 1
+
+					/* IDSEL 15 */
+					 7800 0 0 1 40000 32 1
+					 7800 0 0 2 40000 33 1
+					 7800 0 0 3 40000 34 1
+					 7800 0 0 4 40000 31 1
+
+					/* IDSEL 18 */
+					 9000 0 0 1 40000 31 1
+					 9000 0 0 2 40000 32 1
+					 9000 0 0 3 40000 33 1
+					 9000 0 0 4 40000 34 1
+
+					/* IDSEL 19 */
+					 9800 0 0 1 40000 34 1
+					 9800 0 0 2 40000 31 1
+					 9800 0 0 3 40000 32 1
+					 9800 0 0 4 40000 33 1
+
+					/* IDSEL 20 */
+					 a000 0 0 1 40000 33 1
+					 a000 0 0 2 40000 34 1
+					 a000 0 0 3 40000 31 1
+					 a000 0 0 4 40000 32 1
+
+					/* IDSEL 21 */
+					 a800 0 0 1 40000 32 1
+					 a800 0 0 2 40000 33 1
+					 a800 0 0 3 40000 34 1
+					 a800 0 0 4 40000 31 1>;
+
+			interrupt-parent = <40000>;
+			interrupts = <42 0>;
+			bus-range = <0 0>;
+			ranges = <02000000 0 80000000 80000000 0 20000000
+				  01000000 0 00000000 e2000000 0 01000000>;
+		};
+
+		pic@40000 {
+			linux,phandle = <40000>;
+			interrupt-controller;
+			#address-cells = <0>;
+			#interrupt-cells = <2>;
+			reg = <40000 20100>;
+			built-in;
+			device_type = "open-pic";
+		};
+
+		cpm@e0000000 {
+			linux,phandle = <e0000000>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+			#interrupt-cells = <2>;
+			device_type = "cpm";
+			model = "CPM2";
+			ranges = <0 0 c0000>;
+			reg = <80000 40000>;
+			command-proc = <919c0>;
+			brg-frequency = <9d5b340>;
+
+			pic@90c00 {
+				linux,phandle = <90c00>;
+				interrupt-controller;
+				#address-cells = <0>;
+				#interrupt-cells = <2>;
+				interrupts = <1e 0>;
+				interrupt-parent = <40000>;
+				reg = <90c00 80>;
+				built-in;
+				device_type = "cpm-pic";
+			};
+
+			scc@91a00 {
+				device_type = "serial";
+				compatible = "cpm_uart";
+				model = "SCC";
+				device-id = <2>;
+				reg = <91a00 20 88000 100>;
+				clock-setup = <00ffffff 0>;
+				rx-clock = <1>;
+				tx-clock = <1>;
+				current-speed = <1c200>;
+				interrupts = <64 1>;
+				interrupt-parent = <90c00>;
+			};
+
+			scc@91a20 {
+				device_type = "serial";
+				compatible = "cpm_uart";
+				model = "SCC";
+				device-id = <3>;
+				reg = <91a20 20 88100 100>;
+				clock-setup = <ff00ffff 90000>;
+				rx-clock = <2>;
+				tx-clock = <2>;
+				current-speed = <1c200>;
+				interrupts = <65 1>;
+				interrupt-parent = <90c00>;
+			};
+
+			fcc@91320 {
+				device_type = "network";
+				compatible = "fs_enet";
+				model = "FCC";
+				device-id = <3>;
+				reg = <91320 20 88500 100 913a0 30>;
+				mac-address = [ 00 00 0C 00 02 FD ];
+				clock-setup = <ff00ffff 250000>;
+				rx-clock = <15>;
+				tx-clock = <16>;
+				interrupts = <5d 1>;
+				interrupt-parent = <90c00>;
+				phy-handle = <2452002>;
+			};
+
+			fcc@91340 {
+				device_type = "network";
+				compatible = "fs_enet";
+				model = "FCC";
+				device-id = <4>;
+				reg = <91340 20 88600 100 913d0 30>;
+				mac-address = [ 00 00 0C 00 03 FD ];
+				clock-setup = <ffff00ff 3700>;
+				rx-clock = <17>;
+				tx-clock = <18>;
+				interrupts = <5e 1>;
+				interrupt-parent = <90c00>;
+				phy-handle = <2452003>;
+			};
+		};
+	};
+};