diff options
| author | Russell King <rmk@dyn-67.arm.linux.org.uk> | 2009-04-16 16:16:34 +0100 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2009-04-16 16:16:34 +0100 |
| commit | 32dc496b47eb31f7a1d115a2708e8ef1d054e1fb (patch) | |
| tree | b0ae57b9b55a0277395934ea75de00f8f54d227a /arch/powerpc/mm | |
| parent | 8cd50e8e2b416c7f07b267ab3457c6c25a540ba9 (diff) | |
| parent | c5ab660db9a98187667d017bb9425f0c1dc76ac1 (diff) | |
Merge branch 'for-rmk' of git://git.pengutronix.de/git/imx/linux-2.6
Diffstat (limited to 'arch/powerpc/mm')
| -rw-r--r-- | arch/powerpc/mm/tlb_nohash.c | 1 | ||||
| -rw-r--r-- | arch/powerpc/mm/tlb_nohash_low.S | 14 |
2 files changed, 13 insertions, 2 deletions
diff --git a/arch/powerpc/mm/tlb_nohash.c b/arch/powerpc/mm/tlb_nohash.c index 7af72970fae..ad2eb4d34dd 100644 --- a/arch/powerpc/mm/tlb_nohash.c +++ b/arch/powerpc/mm/tlb_nohash.c @@ -125,7 +125,6 @@ static void do_flush_tlb_page_ipi(void *param) void flush_tlb_mm(struct mm_struct *mm) { - cpumask_t cpu_mask; unsigned int pid; preempt_disable(); diff --git a/arch/powerpc/mm/tlb_nohash_low.S b/arch/powerpc/mm/tlb_nohash_low.S index 788b87c36f7..45fed369834 100644 --- a/arch/powerpc/mm/tlb_nohash_low.S +++ b/arch/powerpc/mm/tlb_nohash_low.S @@ -138,7 +138,11 @@ BEGIN_MMU_FTR_SECTION andi. r3,r3,MMUCSR0_TLBFI@l bne 1b MMU_FTR_SECTION_ELSE - PPC_TLBILX_ALL(0,0) + BEGIN_MMU_FTR_SECTION_NESTED(96) + PPC_TLBILX_ALL(0,r3) + MMU_FTR_SECTION_ELSE_NESTED(96) + PPC_TLBILX_ALL_EARLY(0,r3) + ALT_MMU_FTR_SECTION_END_NESTED_IFCLR(MMU_FTR_TLBILX_EARLY_OPCODE, 96) ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_USE_TLBILX) msync isync @@ -151,7 +155,11 @@ BEGIN_MMU_FTR_SECTION wrteei 0 mfspr r4,SPRN_MAS6 /* save MAS6 */ mtspr SPRN_MAS6,r3 + BEGIN_MMU_FTR_SECTION_NESTED(96) PPC_TLBILX_PID(0,0) + MMU_FTR_SECTION_ELSE_NESTED(96) + PPC_TLBILX_PID_EARLY(0,0) + ALT_MMU_FTR_SECTION_END_NESTED_IFCLR(MMU_FTR_TLBILX_EARLY_OPCODE, 96) mtspr SPRN_MAS6,r4 /* restore MAS6 */ wrtee r10 MMU_FTR_SECTION_ELSE @@ -185,7 +193,11 @@ BEGIN_MMU_FTR_SECTION mtspr SPRN_MAS1,r4 tlbwe MMU_FTR_SECTION_ELSE + BEGIN_MMU_FTR_SECTION_NESTED(96) PPC_TLBILX_VA(0,r3) + MMU_FTR_SECTION_ELSE_NESTED(96) + PPC_TLBILX_VA_EARLY(0,r3) + ALT_MMU_FTR_SECTION_END_NESTED_IFCLR(MMU_FTR_TLBILX_EARLY_OPCODE, 96) ALT_MMU_FTR_SECTION_END_IFCLR(MMU_FTR_USE_TLBILX) msync isync |