aboutsummaryrefslogtreecommitdiff
path: root/arch/powerpc/sysdev/indirect_pci.c
diff options
context:
space:
mode:
authorLinus Torvalds <torvalds@woody.linux-foundation.org>2007-07-24 20:26:25 -0700
committerLinus Torvalds <torvalds@woody.linux-foundation.org>2007-07-24 20:26:25 -0700
commit0de085bb474f64e4fdb2f1ff3268590792648c7b (patch)
tree67c88c8215b85e01430531dba7d7c8ad73173b67 /arch/powerpc/sysdev/indirect_pci.c
parent3836df6b520a2f93033bf53200b12a2cb5137395 (diff)
parente58712111fe6eb7573fd6dd12d80de3bec13f277 (diff)
Merge branch 'for_paulus' of master.kernel.org:/pub/scm/linux/kernel/git/galak/powerpc
* 'for_paulus' of master.kernel.org:/pub/scm/linux/kernel/git/galak/powerpc: (25 commits) [POWERPC] 85xx: Added needed MPC85xx PCI device IDs [POWERPC] Add Freescale PCI VENDOR ID and 8641 device IDs [POWERPC] 85xxCDS: MPC8548 DTS cleanup. [POWERPC] 85xxCDS: Misc 8548 PCI Corrections. [POWERPC] 85xxCDS: Delay 8259 cascade hookup. [POWERPC] 85xxCDS: Make sure restart resets the PCI bus. [POWERPC] 85xxCDS: Allow 8259 cascade to share an MPIC interrupt line. [POWERPC] FSL: Add support for PCI-X controllers [POWERPC] Make sure virtual P2P bridge registers are setup on PCIe PHB [POWERPC] Provide ability to setup P2P bridge registers from struct resource [POWERPC] Add basic PCI/PCI Express support for 8544DS board [POWERPC] Make endianess of cfg_addr for indirect pci ops runtime [POWERPC] Removed setup_indirect_pci_nomap [POWERPC] 85xx: Add quirk to ignore bogus FPGA on CDS [POWERPC] 85xx: Added 8568 PCIe support [POWERPC] Fixup resources on pci_bus for PCIe PHB when no device is connected [POWERPC] Add basic PCI node for mpc8568mds board [POWERPC] Use Freescale pci/pcie common code for 85xx boards [POWERPC] Update PCI nodes in the 83xx/85xx boards device tree [POWERPC] Add 8548 CDS PCI express controller node and PCI-X device node ...
Diffstat (limited to 'arch/powerpc/sysdev/indirect_pci.c')
-rw-r--r--arch/powerpc/sysdev/indirect_pci.c59
1 files changed, 32 insertions, 27 deletions
diff --git a/arch/powerpc/sysdev/indirect_pci.c b/arch/powerpc/sysdev/indirect_pci.c
index c7e6e859b39..a8ac2dfdd3d 100644
--- a/arch/powerpc/sysdev/indirect_pci.c
+++ b/arch/powerpc/sysdev/indirect_pci.c
@@ -20,12 +20,6 @@
#include <asm/pci-bridge.h>
#include <asm/machdep.h>
-#ifdef CONFIG_PPC_INDIRECT_PCI_BE
-#define PCI_CFG_OUT out_be32
-#else
-#define PCI_CFG_OUT out_le32
-#endif
-
static int
indirect_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
int len, u32 *val)
@@ -35,10 +29,17 @@ indirect_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
u8 cfg_type = 0;
u32 bus_no, reg;
+ if (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK) {
+ if (bus->number != hose->first_busno)
+ return PCIBIOS_DEVICE_NOT_FOUND;
+ if (devfn != 0)
+ return PCIBIOS_DEVICE_NOT_FOUND;
+ }
+
if (ppc_md.pci_exclude_device)
if (ppc_md.pci_exclude_device(hose, bus->number, devfn))
return PCIBIOS_DEVICE_NOT_FOUND;
-
+
if (hose->indirect_type & PPC_INDIRECT_TYPE_SET_CFG_TYPE)
if (bus->number != hose->first_busno)
cfg_type = 1;
@@ -51,9 +52,12 @@ indirect_read_config(struct pci_bus *bus, unsigned int devfn, int offset,
else
reg = offset & 0xfc;
- PCI_CFG_OUT(hose->cfg_addr,
- (0x80000000 | (bus_no << 16)
- | (devfn << 8) | reg | cfg_type));
+ if (hose->indirect_type & PPC_INDIRECT_TYPE_BIG_ENDIAN)
+ out_be32(hose->cfg_addr, (0x80000000 | (bus_no << 16) |
+ (devfn << 8) | reg | cfg_type));
+ else
+ out_le32(hose->cfg_addr, (0x80000000 | (bus_no << 16) |
+ (devfn << 8) | reg | cfg_type));
/*
* Note: the caller has already checked that offset is
@@ -83,6 +87,13 @@ indirect_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
u8 cfg_type = 0;
u32 bus_no, reg;
+ if (hose->indirect_type & PPC_INDIRECT_TYPE_NO_PCIE_LINK) {
+ if (bus->number != hose->first_busno)
+ return PCIBIOS_DEVICE_NOT_FOUND;
+ if (devfn != 0)
+ return PCIBIOS_DEVICE_NOT_FOUND;
+ }
+
if (ppc_md.pci_exclude_device)
if (ppc_md.pci_exclude_device(hose, bus->number, devfn))
return PCIBIOS_DEVICE_NOT_FOUND;
@@ -99,9 +110,12 @@ indirect_write_config(struct pci_bus *bus, unsigned int devfn, int offset,
else
reg = offset & 0xfc;
- PCI_CFG_OUT(hose->cfg_addr,
- (0x80000000 | (bus_no << 16)
- | (devfn << 8) | reg | cfg_type));
+ if (hose->indirect_type & PPC_INDIRECT_TYPE_BIG_ENDIAN)
+ out_be32(hose->cfg_addr, (0x80000000 | (bus_no << 16) |
+ (devfn << 8) | reg | cfg_type));
+ else
+ out_le32(hose->cfg_addr, (0x80000000 | (bus_no << 16) |
+ (devfn << 8) | reg | cfg_type));
/* surpress setting of PCI_PRIMARY_BUS */
if (hose->indirect_type & PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS)
@@ -135,24 +149,15 @@ static struct pci_ops indirect_pci_ops =
};
void __init
-setup_indirect_pci_nomap(struct pci_controller* hose, void __iomem * cfg_addr,
- void __iomem * cfg_data)
-{
- hose->cfg_addr = cfg_addr;
- hose->cfg_data = cfg_data;
- hose->ops = &indirect_pci_ops;
-}
-
-void __init
-setup_indirect_pci(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data)
+setup_indirect_pci(struct pci_controller* hose, u32 cfg_addr, u32 cfg_data, u32 flags)
{
unsigned long base = cfg_addr & PAGE_MASK;
- void __iomem *mbase, *addr, *data;
+ void __iomem *mbase;
mbase = ioremap(base, PAGE_SIZE);
- addr = mbase + (cfg_addr & ~PAGE_MASK);
+ hose->cfg_addr = mbase + (cfg_addr & ~PAGE_MASK);
if ((cfg_data & PAGE_MASK) != base)
mbase = ioremap(cfg_data & PAGE_MASK, PAGE_SIZE);
- data = mbase + (cfg_data & ~PAGE_MASK);
- setup_indirect_pci_nomap(hose, addr, data);
+ hose->cfg_data = mbase + (cfg_data & ~PAGE_MASK);
+ hose->ops = &indirect_pci_ops;
}