diff options
author | Linus Torvalds <torvalds@woody.linux-foundation.org> | 2007-10-11 21:55:47 -0700 |
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committer | Linus Torvalds <torvalds@woody.linux-foundation.org> | 2007-10-11 21:55:47 -0700 |
commit | e86908614f2c7fec401827e5cefd7a6ea9407f85 (patch) | |
tree | fcb5d9e52422b37bdaf0e647126ebdfc1680f162 /arch/powerpc/sysdev/qe_lib/ucc.c | |
parent | 547307420931344a868275bd7ea7a30f117a15a9 (diff) | |
parent | 9b4b8feb962f4b3e74768b7205f1f8f6cce87238 (diff) |
Merge branch 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/paulus/powerpc
* 'master' of git://git.kernel.org/pub/scm/linux/kernel/git/paulus/powerpc: (408 commits)
[POWERPC] Add memchr() to the bootwrapper
[POWERPC] Implement logging of unhandled signals
[POWERPC] Add legacy serial support for OPB with flattened device tree
[POWERPC] Use 1TB segments
[POWERPC] XilinxFB: Allow fixed framebuffer base address
[POWERPC] XilinxFB: Add support for custom screen resolution
[POWERPC] XilinxFB: Use pdata to pass around framebuffer parameters
[POWERPC] PCI: Add 64-bit physical address support to setup_indirect_pci
[POWERPC] 4xx: Kilauea defconfig file
[POWERPC] 4xx: Kilauea DTS
[POWERPC] 4xx: Add AMCC Kilauea eval board support to platforms/40x
[POWERPC] 4xx: Add AMCC 405EX support to cputable.c
[POWERPC] Adjust TASK_SIZE on ppc32 systems to 3GB that are capable
[POWERPC] Use PAGE_OFFSET to tell if an address is user/kernel in SW TLB handlers
[POWERPC] 85xx: Enable FP emulation in MPC8560 ADS defconfig
[POWERPC] 85xx: Killed <asm/mpc85xx.h>
[POWERPC] 85xx: Add cpm nodes for 8541/8555 CDS
[POWERPC] 85xx: Convert mpc8560ads to the new CPM binding.
[POWERPC] mpc8272ads: Remove muram from the CPM reg property.
[POWERPC] Make clockevents work on PPC601 processors
...
Fixed up conflict in Documentation/powerpc/booting-without-of.txt manually.
Diffstat (limited to 'arch/powerpc/sysdev/qe_lib/ucc.c')
-rw-r--r-- | arch/powerpc/sysdev/qe_lib/ucc.c | 270 |
1 files changed, 115 insertions, 155 deletions
diff --git a/arch/powerpc/sysdev/qe_lib/ucc.c b/arch/powerpc/sysdev/qe_lib/ucc.c index f970e5415ac..0e348d9af8a 100644 --- a/arch/powerpc/sysdev/qe_lib/ucc.c +++ b/arch/powerpc/sysdev/qe_lib/ucc.c @@ -28,228 +28,188 @@ static DEFINE_SPINLOCK(ucc_lock); -int ucc_set_qe_mux_mii_mng(int ucc_num) +int ucc_set_qe_mux_mii_mng(unsigned int ucc_num) { unsigned long flags; + if (ucc_num > UCC_MAX_NUM - 1) + return -EINVAL; + spin_lock_irqsave(&ucc_lock, flags); - out_be32(&qe_immr->qmx.cmxgcr, - ((in_be32(&qe_immr->qmx.cmxgcr) & - ~QE_CMXGCR_MII_ENET_MNG) | - (ucc_num << QE_CMXGCR_MII_ENET_MNG_SHIFT))); + clrsetbits_be32(&qe_immr->qmx.cmxgcr, QE_CMXGCR_MII_ENET_MNG, + ucc_num << QE_CMXGCR_MII_ENET_MNG_SHIFT); spin_unlock_irqrestore(&ucc_lock, flags); return 0; } EXPORT_SYMBOL(ucc_set_qe_mux_mii_mng); -int ucc_set_type(int ucc_num, struct ucc_common *regs, - enum ucc_speed_type speed) -{ - u8 guemr = 0; - - /* check if the UCC number is in range. */ - if ((ucc_num > UCC_MAX_NUM - 1) || (ucc_num < 0)) - return -EINVAL; - - guemr = regs->guemr; - guemr &= ~(UCC_GUEMR_MODE_MASK_RX | UCC_GUEMR_MODE_MASK_TX); - switch (speed) { - case UCC_SPEED_TYPE_SLOW: - guemr |= (UCC_GUEMR_MODE_SLOW_RX | UCC_GUEMR_MODE_SLOW_TX); - break; - case UCC_SPEED_TYPE_FAST: - guemr |= (UCC_GUEMR_MODE_FAST_RX | UCC_GUEMR_MODE_FAST_TX); - break; - default: - return -EINVAL; - } - regs->guemr = guemr; - - return 0; -} - -int ucc_init_guemr(struct ucc_common *regs) +/* Configure the UCC to either Slow or Fast. + * + * A given UCC can be figured to support either "slow" devices (e.g. UART) + * or "fast" devices (e.g. Ethernet). + * + * 'ucc_num' is the UCC number, from 0 - 7. + * + * This function also sets the UCC_GUEMR_SET_RESERVED3 bit because that bit + * must always be set to 1. + */ +int ucc_set_type(unsigned int ucc_num, enum ucc_speed_type speed) { - u8 guemr = 0; - - if (!regs) - return -EINVAL; - - /* Set bit 3 (which is reserved in the GUEMR register) to 1 */ - guemr = UCC_GUEMR_SET_RESERVED3; - - regs->guemr = guemr; - - return 0; -} + u8 __iomem *guemr; -static void get_cmxucr_reg(int ucc_num, volatile u32 ** p_cmxucr, u8 * reg_num, - u8 * shift) -{ + /* The GUEMR register is at the same location for both slow and fast + devices, so we just use uccX.slow.guemr. */ switch (ucc_num) { - case 0: *p_cmxucr = &(qe_immr->qmx.cmxucr1); - *reg_num = 1; - *shift = 16; + case 0: guemr = &qe_immr->ucc1.slow.guemr; break; - case 2: *p_cmxucr = &(qe_immr->qmx.cmxucr1); - *reg_num = 1; - *shift = 0; + case 1: guemr = &qe_immr->ucc2.slow.guemr; break; - case 4: *p_cmxucr = &(qe_immr->qmx.cmxucr2); - *reg_num = 2; - *shift = 16; + case 2: guemr = &qe_immr->ucc3.slow.guemr; break; - case 6: *p_cmxucr = &(qe_immr->qmx.cmxucr2); - *reg_num = 2; - *shift = 0; + case 3: guemr = &qe_immr->ucc4.slow.guemr; break; - case 1: *p_cmxucr = &(qe_immr->qmx.cmxucr3); - *reg_num = 3; - *shift = 16; + case 4: guemr = &qe_immr->ucc5.slow.guemr; break; - case 3: *p_cmxucr = &(qe_immr->qmx.cmxucr3); - *reg_num = 3; - *shift = 0; + case 5: guemr = &qe_immr->ucc6.slow.guemr; break; - case 5: *p_cmxucr = &(qe_immr->qmx.cmxucr4); - *reg_num = 4; - *shift = 16; + case 6: guemr = &qe_immr->ucc7.slow.guemr; break; - case 7: *p_cmxucr = &(qe_immr->qmx.cmxucr4); - *reg_num = 4; - *shift = 0; + case 7: guemr = &qe_immr->ucc8.slow.guemr; break; default: - break; + return -EINVAL; } + + clrsetbits_8(guemr, UCC_GUEMR_MODE_MASK, + UCC_GUEMR_SET_RESERVED3 | speed); + + return 0; +} + +static void get_cmxucr_reg(unsigned int ucc_num, __be32 **cmxucr, + unsigned int *reg_num, unsigned int *shift) +{ + unsigned int cmx = ((ucc_num & 1) << 1) + (ucc_num > 3); + + *reg_num = cmx + 1; + *cmxucr = &qe_immr->qmx.cmxucr[cmx]; + *shift = 16 - 8 * (ucc_num & 2); } -int ucc_mux_set_grant_tsa_bkpt(int ucc_num, int set, u32 mask) +int ucc_mux_set_grant_tsa_bkpt(unsigned int ucc_num, int set, u32 mask) { - volatile u32 *p_cmxucr; - u8 reg_num; - u8 shift; + __be32 *cmxucr; + unsigned int reg_num; + unsigned int shift; /* check if the UCC number is in range. */ - if ((ucc_num > UCC_MAX_NUM - 1) || (ucc_num < 0)) + if (ucc_num > UCC_MAX_NUM - 1) return -EINVAL; - get_cmxucr_reg(ucc_num, &p_cmxucr, ®_num, &shift); + get_cmxucr_reg(ucc_num, &cmxucr, ®_num, &shift); if (set) - out_be32(p_cmxucr, in_be32(p_cmxucr) | (mask << shift)); + setbits32(cmxucr, mask << shift); else - out_be32(p_cmxucr, in_be32(p_cmxucr) & ~(mask << shift)); + clrbits32(cmxucr, mask << shift); return 0; } -int ucc_set_qe_mux_rxtx(int ucc_num, enum qe_clock clock, enum comm_dir mode) +int ucc_set_qe_mux_rxtx(unsigned int ucc_num, enum qe_clock clock, + enum comm_dir mode) { - volatile u32 *p_cmxucr; - u8 reg_num; - u8 shift; - u32 clock_bits; - u32 clock_mask; - int source = -1; + __be32 *cmxucr; + unsigned int reg_num; + unsigned int shift; + u32 clock_bits = 0; /* check if the UCC number is in range. */ - if ((ucc_num > UCC_MAX_NUM - 1) || (ucc_num < 0)) + if (ucc_num > UCC_MAX_NUM - 1) return -EINVAL; - if (!((mode == COMM_DIR_RX) || (mode == COMM_DIR_TX))) { - printk(KERN_ERR - "ucc_set_qe_mux_rxtx: bad comm mode type passed."); + /* The communications direction must be RX or TX */ + if (!((mode == COMM_DIR_RX) || (mode == COMM_DIR_TX))) return -EINVAL; - } - get_cmxucr_reg(ucc_num, &p_cmxucr, ®_num, &shift); + get_cmxucr_reg(ucc_num, &cmxucr, ®_num, &shift); switch (reg_num) { case 1: switch (clock) { - case QE_BRG1: source = 1; break; - case QE_BRG2: source = 2; break; - case QE_BRG7: source = 3; break; - case QE_BRG8: source = 4; break; - case QE_CLK9: source = 5; break; - case QE_CLK10: source = 6; break; - case QE_CLK11: source = 7; break; - case QE_CLK12: source = 8; break; - case QE_CLK15: source = 9; break; - case QE_CLK16: source = 10; break; - default: source = -1; break; + case QE_BRG1: clock_bits = 1; break; + case QE_BRG2: clock_bits = 2; break; + case QE_BRG7: clock_bits = 3; break; + case QE_BRG8: clock_bits = 4; break; + case QE_CLK9: clock_bits = 5; break; + case QE_CLK10: clock_bits = 6; break; + case QE_CLK11: clock_bits = 7; break; + case QE_CLK12: clock_bits = 8; break; + case QE_CLK15: clock_bits = 9; break; + case QE_CLK16: clock_bits = 10; break; + default: break; } break; case 2: switch (clock) { - case QE_BRG5: source = 1; break; - case QE_BRG6: source = 2; break; - case QE_BRG7: source = 3; break; - case QE_BRG8: source = 4; break; - case QE_CLK13: source = 5; break; - case QE_CLK14: source = 6; break; - case QE_CLK19: source = 7; break; - case QE_CLK20: source = 8; break; - case QE_CLK15: source = 9; break; - case QE_CLK16: source = 10; break; - default: source = -1; break; + case QE_BRG5: clock_bits = 1; break; + case QE_BRG6: clock_bits = 2; break; + case QE_BRG7: clock_bits = 3; break; + case QE_BRG8: clock_bits = 4; break; + case QE_CLK13: clock_bits = 5; break; + case QE_CLK14: clock_bits = 6; break; + case QE_CLK19: clock_bits = 7; break; + case QE_CLK20: clock_bits = 8; break; + case QE_CLK15: clock_bits = 9; break; + case QE_CLK16: clock_bits = 10; break; + default: break; } break; case 3: switch (clock) { - case QE_BRG9: source = 1; break; - case QE_BRG10: source = 2; break; - case QE_BRG15: source = 3; break; - case QE_BRG16: source = 4; break; - case QE_CLK3: source = 5; break; - case QE_CLK4: source = 6; break; - case QE_CLK17: source = 7; break; - case QE_CLK18: source = 8; break; - case QE_CLK7: source = 9; break; - case QE_CLK8: source = 10; break; - case QE_CLK16: source = 11; break; - default: source = -1; break; + case QE_BRG9: clock_bits = 1; break; + case QE_BRG10: clock_bits = 2; break; + case QE_BRG15: clock_bits = 3; break; + case QE_BRG16: clock_bits = 4; break; + case QE_CLK3: clock_bits = 5; break; + case QE_CLK4: clock_bits = 6; break; + case QE_CLK17: clock_bits = 7; break; + case QE_CLK18: clock_bits = 8; break; + case QE_CLK7: clock_bits = 9; break; + case QE_CLK8: clock_bits = 10; break; + case QE_CLK16: clock_bits = 11; break; + default: break; } break; case 4: switch (clock) { - case QE_BRG13: source = 1; break; - case QE_BRG14: source = 2; break; - case QE_BRG15: source = 3; break; - case QE_BRG16: source = 4; break; - case QE_CLK5: source = 5; break; - case QE_CLK6: source = 6; break; - case QE_CLK21: source = 7; break; - case QE_CLK22: source = 8; break; - case QE_CLK7: source = 9; break; - case QE_CLK8: source = 10; break; - case QE_CLK16: source = 11; break; - default: source = -1; break; + case QE_BRG13: clock_bits = 1; break; + case QE_BRG14: clock_bits = 2; break; + case QE_BRG15: clock_bits = 3; break; + case QE_BRG16: clock_bits = 4; break; + case QE_CLK5: clock_bits = 5; break; + case QE_CLK6: clock_bits = 6; break; + case QE_CLK21: clock_bits = 7; break; + case QE_CLK22: clock_bits = 8; break; + case QE_CLK7: clock_bits = 9; break; + case QE_CLK8: clock_bits = 10; break; + case QE_CLK16: clock_bits = 11; break; + default: break; } break; - default: - source = -1; - break; + default: break; } - if (source == -1) { - printk(KERN_ERR - "ucc_set_qe_mux_rxtx: Bad combination of clock and UCC."); + /* Check for invalid combination of clock and UCC number */ + if (!clock_bits) return -ENOENT; - } - clock_bits = (u32) source; - clock_mask = QE_CMXUCR_TX_CLK_SRC_MASK; - if (mode == COMM_DIR_RX) { - clock_bits <<= 4; /* Rx field is 4 bits to left of Tx field */ - clock_mask <<= 4; /* Rx field is 4 bits to left of Tx field */ - } - clock_bits <<= shift; - clock_mask <<= shift; + if (mode == COMM_DIR_RX) + shift += 4; - out_be32(p_cmxucr, (in_be32(p_cmxucr) & ~clock_mask) | clock_bits); + clrsetbits_be32(cmxucr, QE_CMXUCR_TX_CLK_SRC_MASK << shift, + clock_bits << shift); return 0; } |