Merge git://git.kernel.org/pub/scm/linux/kernel/git/paulus/powerpc

12 files changed, 670 insertions, 191 deletions

diff --git a/arch/ppc/platforms/4xx/Kconfig b/arch/ppc/platforms/4xx/Kconfig
index d8837911bbc..174ddbc9758 100644
--- a/arch/ppc/platforms/4xx/Kconfig
+++ b/arch/ppc/platforms/4xx/Kconfig
@@ -57,6 +57,10 @@ config XILINX_ML300
 	help
 	  This option enables support for the Xilinx ML300 evaluation board.
 
+config XILINX_ML403
+	bool "Xilinx-ML403"
+	help
+	  This option enables support for the Xilinx ML403 evaluation board.
 endchoice
 
 choice
@@ -172,11 +176,6 @@ config IBM_OCP
 	depends on ASH || BAMBOO || BUBINGA || CPCI405 || EBONY || EP405 || LUAN || YUCCA || OCOTEA || REDWOOD_5 || REDWOOD_6 || SYCAMORE || WALNUT
 	default y
 
-config XILINX_OCP
-	bool
-	depends on XILINX_ML300
-	default y
-
 config IBM_EMAC4
 	bool
 	depends on 440GX || 440SP || 440SPE
@@ -208,11 +207,21 @@ config 405GPR
 	depends on SYCAMORE
 	default y
 
-config VIRTEX_II_PRO
+config XILINX_VIRTEX_II_PRO
 	bool
 	depends on XILINX_ML300
 	default y
 
+config XILINX_VIRTEX_4_FX
+	bool
+	depends on XILINX_ML403
+	default y
+
+config XILINX_VIRTEX
+	bool
+	depends on XILINX_VIRTEX_II_PRO || XILINX_VIRTEX_4_FX
+	default y
+
 config STB03xxx
 	bool
 	depends on REDWOOD_5 || REDWOOD_6
@@ -220,7 +229,7 @@ config STB03xxx
 
 config EMBEDDEDBOOT
 	bool
-	depends on EP405 || XILINX_ML300
+	depends on EP405 || XILINX_ML300 || XILINX_ML403
 	default y
 
 config IBM_OPENBIOS
diff --git a/arch/ppc/platforms/4xx/Makefile b/arch/ppc/platforms/4xx/Makefile
index c9bb6117095..a04a0d0a0f5 100644
--- a/arch/ppc/platforms/4xx/Makefile
+++ b/arch/ppc/platforms/4xx/Makefile
@@ -14,6 +14,7 @@ obj-$(CONFIG_REDWOOD_6)		+= redwood6.o
 obj-$(CONFIG_SYCAMORE)		+= sycamore.o
 obj-$(CONFIG_WALNUT)		+= walnut.o
 obj-$(CONFIG_XILINX_ML300)	+= xilinx_ml300.o
+obj-$(CONFIG_XILINX_ML403)	+= xilinx_ml403.o
 
 obj-$(CONFIG_405GP)		+= ibm405gp.o
 obj-$(CONFIG_REDWOOD_5)		+= ibmstb4.o
@@ -26,4 +27,5 @@ obj-$(CONFIG_440SP)		+= ibm440sp.o
 obj-$(CONFIG_440SPE)		+= ppc440spe.o
 obj-$(CONFIG_405EP)		+= ibm405ep.o
 obj-$(CONFIG_405GPR)		+= ibm405gpr.o
-obj-$(CONFIG_VIRTEX_II_PRO)	+= virtex-ii_pro.o
+obj-$(CONFIG_XILINX_VIRTEX)	+= virtex.o
+
diff --git a/arch/ppc/platforms/4xx/virtex-ii_pro.c b/arch/ppc/platforms/4xx/virtex-ii_pro.c
deleted file mode 100644
index 097cc9d5aca..00000000000
--- a/arch/ppc/platforms/4xx/virtex-ii_pro.c
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- * arch/ppc/platforms/4xx/virtex-ii_pro.c
- *
- * Author: MontaVista Software, Inc.
- *         source@mvista.com
- *
- * 2002-2004 (c) MontaVista Software, Inc.  This file is licensed under the
- * terms of the GNU General Public License version 2.  This program is licensed
- * "as is" without any warranty of any kind, whether express or implied.
- */
-
-#include <linux/config.h>
-#include <linux/init.h>
-#include <asm/ocp.h>
-#include "virtex-ii_pro.h"
-
-/* Have OCP take care of the serial ports. */
-struct ocp_def core_ocp[] = {
-#ifdef XPAR_UARTNS550_0_BASEADDR
-	{ .vendor	= OCP_VENDOR_XILINX,
-	  .function	= OCP_FUNC_16550,
-	  .index	= 0,
-	  .paddr	= XPAR_UARTNS550_0_BASEADDR,
-	  .irq		= XPAR_INTC_0_UARTNS550_0_VEC_ID,
-	  .pm		= OCP_CPM_NA
-	},
-#ifdef XPAR_UARTNS550_1_BASEADDR
-	{ .vendor	= OCP_VENDOR_XILINX,
-	  .function	= OCP_FUNC_16550,
-	  .index	= 1,
-	  .paddr	= XPAR_UARTNS550_1_BASEADDR,
-	  .irq		= XPAR_INTC_0_UARTNS550_1_VEC_ID,
-	  .pm		= OCP_CPM_NA
-	},
-#ifdef XPAR_UARTNS550_2_BASEADDR
-	{ .vendor	= OCP_VENDOR_XILINX,
-	  .function	= OCP_FUNC_16550,
-	  .index	= 2,
-	  .paddr	= XPAR_UARTNS550_2_BASEADDR,
-	  .irq		= XPAR_INTC_0_UARTNS550_2_VEC_ID,
-	  .pm		= OCP_CPM_NA
-	},
-#ifdef XPAR_UARTNS550_3_BASEADDR
-	{ .vendor	= OCP_VENDOR_XILINX,
-	  .function	= OCP_FUNC_16550,
-	  .index	= 3,
-	  .paddr	= XPAR_UARTNS550_3_BASEADDR,
-	  .irq		= XPAR_INTC_0_UARTNS550_3_VEC_ID,
-	  .pm		= OCP_CPM_NA
-	},
-#ifdef XPAR_UARTNS550_4_BASEADDR
-#error Edit this file to add more devices.
-#endif			/* 4 */
-#endif			/* 3 */
-#endif			/* 2 */
-#endif			/* 1 */
-#endif			/* 0 */
-	{ .vendor	= OCP_VENDOR_INVALID
-	}
-};
diff --git a/arch/ppc/platforms/4xx/virtex-ii_pro.h b/arch/ppc/platforms/4xx/virtex-ii_pro.h
deleted file mode 100644
index 9014c488733..00000000000
--- a/arch/ppc/platforms/4xx/virtex-ii_pro.h
+++ /dev/null
@@ -1,99 +0,0 @@
-/*
- * arch/ppc/platforms/4xx/virtex-ii_pro.h
- *
- * Include file that defines the Xilinx Virtex-II Pro processor
- *
- * Author: MontaVista Software, Inc.
- *         source@mvista.com
- *
- * 2002-2004 (c) MontaVista Software, Inc.  This file is licensed under the
- * terms of the GNU General Public License version 2.  This program is licensed
- * "as is" without any warranty of any kind, whether express or implied.
- */
-
-#ifdef __KERNEL__
-#ifndef __ASM_VIRTEXIIPRO_H__
-#define __ASM_VIRTEXIIPRO_H__
-
-#include <linux/config.h>
-#include <asm/xparameters.h>
-
-/* serial defines */
-
-#define RS_TABLE_SIZE  4	/* change this and add more devices below
-				   if you have more then 4 16x50 UARTs */
-
-#define BASE_BAUD		(XPAR_UARTNS550_0_CLOCK_FREQ_HZ/16)
-
-/* The serial ports in the Virtex-II Pro have each I/O byte in the
- * LSByte of a word.  This means that iomem_reg_shift needs to be 2 to
- * change the byte offsets into word offsets.  In addition the base
- * addresses need to have 3 added to them to get to the LSByte.
- */
-#define STD_UART_OP(num)						 \
-	{ 0, BASE_BAUD, 0, XPAR_INTC_0_UARTNS550_##num##_VEC_ID,	 \
-		ASYNC_BOOT_AUTOCONF,		 			 \
-		.iomem_base = (u8 *)XPAR_UARTNS550_##num##_BASEADDR + 3, \
-		.iomem_reg_shift = 2,					 \
-		.io_type = SERIAL_IO_MEM},
-
-#if defined(XPAR_INTC_0_UARTNS550_0_VEC_ID)
-#define ML300_UART0 STD_UART_OP(0)
-#else
-#define ML300_UART0
-#endif
-
-#if defined(XPAR_INTC_0_UARTNS550_1_VEC_ID)
-#define ML300_UART1 STD_UART_OP(1)
-#else
-#define ML300_UART1
-#endif
-
-#if defined(XPAR_INTC_0_UARTNS550_2_VEC_ID)
-#define ML300_UART2 STD_UART_OP(2)
-#else
-#define ML300_UART2
-#endif
-
-#if defined(XPAR_INTC_0_UARTNS550_3_VEC_ID)
-#define ML300_UART3 STD_UART_OP(3)
-#else
-#define ML300_UART3
-#endif
-
-#if defined(XPAR_INTC_0_UARTNS550_4_VEC_ID)
-#error Edit this file to add more devices.
-#elif defined(XPAR_INTC_0_UARTNS550_3_VEC_ID)
-#define NR_SER_PORTS	4
-#elif defined(XPAR_INTC_0_UARTNS550_2_VEC_ID)
-#define NR_SER_PORTS	3
-#elif defined(XPAR_INTC_0_UARTNS550_1_VEC_ID)
-#define NR_SER_PORTS	2
-#elif defined(XPAR_INTC_0_UARTNS550_0_VEC_ID)
-#define NR_SER_PORTS	1
-#else
-#define NR_SER_PORTS	0
-#endif
-
-#if defined(CONFIG_UART0_TTYS0)
-#define SERIAL_PORT_DFNS	\
-	ML300_UART0		\
-	ML300_UART1		\
-	ML300_UART2		\
-	ML300_UART3
-#endif
-
-#if defined(CONFIG_UART0_TTYS1)
-#define SERIAL_PORT_DFNS	\
-	ML300_UART1		\
-	ML300_UART0		\
-	ML300_UART2		\
-	ML300_UART3
-#endif
-
-#define DCRN_CPMFR_BASE	0
-
-#include <asm/ibm405.h>
-
-#endif				/* __ASM_VIRTEXIIPRO_H__ */
-#endif				/* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/virtex.c b/arch/ppc/platforms/4xx/virtex.c
new file mode 100644
index 00000000000..133a8314719
--- /dev/null
+++ b/arch/ppc/platforms/4xx/virtex.c
@@ -0,0 +1,56 @@
+/*
+ * Virtex-II Pro & Virtex-4 FX common infrastructure
+ *
+ * Maintainer: Grant Likely <grant.likely@secretlab.ca>
+ *
+ * Copyright 2005 Secret Lab Technologies Ltd.
+ * Copyright 2005 General Dynamics Canada Ltd.
+ * Copyright 2005 Freescale Semiconductor Inc.
+ *
+ * This program is free software; you can redistribute  it and/or modify it
+ * under  the terms of  the GNU General  Public License as published by the
+ * Free Software Foundation;  either version 2 of the  License, or (at your
+ * option) any later version.
+ */
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/device.h>
+#include <linux/serial_8250.h>
+#include <asm/ppc_sys.h>
+#include <platforms/4xx/virtex.h>
+#include <platforms/4xx/xparameters/xparameters.h>
+
+#define XPAR_UART(num) { \
+		.mapbase  = XPAR_UARTNS550_##num##_BASEADDR + 3, \
+		.irq	  = XPAR_INTC_0_UARTNS550_##num##_VEC_ID, \
+		.iotype	  = UPIO_MEM, \
+		.uartclk  = XPAR_UARTNS550_##num##_CLOCK_FREQ_HZ, \
+		.flags	  = UPF_BOOT_AUTOCONF, \
+		.regshift = 2, \
+	}
+
+struct plat_serial8250_port serial_platform_data[] = {
+#ifdef XPAR_UARTNS550_0_BASEADDR
+	XPAR_UART(0),
+#endif
+#ifdef XPAR_UARTNS550_1_BASEADDR
+	XPAR_UART(1),
+#endif
+#ifdef XPAR_UARTNS550_2_BASEADDR
+	XPAR_UART(2),
+#endif
+#ifdef XPAR_UARTNS550_3_BASEADDR
+	XPAR_UART(3),
+#endif
+	{ }, /* terminated by empty record */
+};
+
+struct platform_device ppc_sys_platform_devices[] = {
+	[VIRTEX_UART] = {
+		.name		= "serial8250",
+		.id		= 0,
+		.dev.platform_data = serial_platform_data,
+	},
+};
+
diff --git a/arch/ppc/platforms/4xx/virtex.h b/arch/ppc/platforms/4xx/virtex.h
new file mode 100644
index 00000000000..1a01b81cff1
--- /dev/null
+++ b/arch/ppc/platforms/4xx/virtex.h
@@ -0,0 +1,35 @@
+/*
+ * arch/ppc/platforms/4xx/virtex.h
+ *
+ * Include file that defines the Xilinx Virtex-II Pro processor
+ *
+ * Author: MontaVista Software, Inc.
+ *         source@mvista.com
+ *
+ * 2002-2004 (c) MontaVista Software, Inc.  This file is licensed under the
+ * terms of the GNU General Public License version 2.  This program is licensed
+ * "as is" without any warranty of any kind, whether express or implied.
+ */
+
+#ifdef __KERNEL__
+#ifndef __ASM_VIRTEX_H__
+#define __ASM_VIRTEX_H__
+
+/* serial defines */
+
+#include <asm/ibm405.h>
+
+/* Ugly, ugly, ugly! BASE_BAUD defined here to keep 8250.c happy. */
+#if !defined(BASE_BAUD)
+ #define BASE_BAUD		(0) /* dummy value; not used */
+#endif
+  
+/* Device type enumeration for platform bus definitions */
+#ifndef __ASSEMBLY__
+enum ppc_sys_devices {
+	VIRTEX_UART,
+};
+#endif
+  
+#endif				/* __ASM_VIRTEX_H__ */
+#endif				/* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/xilinx_ml300.c b/arch/ppc/platforms/4xx/xilinx_ml300.c
index 0b1b77d986b..267afb50607 100644
--- a/arch/ppc/platforms/4xx/xilinx_ml300.c
+++ b/arch/ppc/platforms/4xx/xilinx_ml300.c
@@ -17,12 +17,14 @@
 #include <linux/tty.h>
 #include <linux/serial.h>
 #include <linux/serial_core.h>
+#include <linux/serial_8250.h>
 #include <linux/serialP.h>
 #include <asm/io.h>
 #include <asm/machdep.h>
-#include <asm/ocp.h>
+#include <asm/ppc_sys.h>
 
-#include <platforms/4xx/virtex-ii_pro.h>	/* for NR_SER_PORTS */
+#include <syslib/gen550.h>
+#include <platforms/4xx/xparameters/xparameters.h>
 
 /*
  * As an overview of how the following functions (platform_init,
@@ -54,6 +56,22 @@
  *          ppc4xx_pic_init			arch/ppc/syslib/xilinx_pic.c
  */
 
+/* Board specifications structures */
+struct ppc_sys_spec *cur_ppc_sys_spec;
+struct ppc_sys_spec ppc_sys_specs[] = {
+	{
+		/* Only one entry, always assume the same design */
+		.ppc_sys_name	= "Xilinx ML300 Reference Design",
+		.mask 		= 0x00000000,
+		.value 		= 0x00000000,
+		.num_devices	= 1,
+		.device_list	= (enum ppc_sys_devices[])
+		{
+			VIRTEX_UART,
+		},
+	},
+};
+
 #if defined(XPAR_POWER_0_POWERDOWN_BASEADDR)
 
 static volatile unsigned *powerdown_base =
@@ -80,28 +98,39 @@ ml300_map_io(void)
 #endif
 }
 
+/* Early serial support functions */
 static void __init
+ml300_early_serial_init(int num, struct plat_serial8250_port *pdata)
+{
+#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
+	struct uart_port serial_req;
+
+	memset(&serial_req, 0, sizeof(serial_req));
+	serial_req.mapbase	= pdata->mapbase;
+	serial_req.membase	= pdata->membase;
+	serial_req.irq		= pdata->irq;
+	serial_req.uartclk	= pdata->uartclk;
+	serial_req.regshift	= pdata->regshift;
+	serial_req.iotype	= pdata->iotype;
+	serial_req.flags	= pdata->flags;
+	gen550_init(num, &serial_req);
+#endif
+}
+
+void __init
 ml300_early_serial_map(void)
 {
 #ifdef CONFIG_SERIAL_8250
-	struct serial_state old_ports[] = { SERIAL_PORT_DFNS };
-	struct uart_port port;
-	int i;
-
-	/* Setup ioremapped serial port access */
-	for (i = 0; i < ARRAY_SIZE(old_ports); i++ ) {
-		memset(&port, 0, sizeof(port));
-		port.membase = ioremap((phys_addr_t)(old_ports[i].iomem_base), 16);
-		port.irq = old_ports[i].irq;
-		port.uartclk = old_ports[i].baud_base * 16;
-		port.regshift = old_ports[i].iomem_reg_shift;
-		port.iotype = SERIAL_IO_MEM;
-		port.flags = ASYNC_BOOT_AUTOCONF | ASYNC_SKIP_TEST;
-		port.line = i;
-
-		if (early_serial_setup(&port) != 0) {
-			printk("Early serial init of port %d failed\n", i);
-		}
+	struct plat_serial8250_port *pdata;
+	int i = 0;
+
+	pdata = (struct plat_serial8250_port *) ppc_sys_get_pdata(VIRTEX_UART);
+	while(pdata && pdata->flags)
+	{
+		pdata->membase = ioremap(pdata->mapbase, 0x100);
+		ml300_early_serial_init(i, pdata);
+		pdata++;
+		i++;
 	}
 #endif /* CONFIG_SERIAL_8250 */
 }
@@ -109,9 +138,8 @@ ml300_early_serial_map(void)
 void __init
 ml300_setup_arch(void)
 {
-	ppc4xx_setup_arch();	/* calls ppc4xx_find_bridges() */
-
 	ml300_early_serial_map();
+	ppc4xx_setup_arch();	/* calls ppc4xx_find_bridges() */
 
 	/* Identify the system */
 	printk(KERN_INFO "Xilinx Virtex-II Pro port\n");
@@ -131,6 +159,8 @@ platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
 {
 	ppc4xx_init(r3, r4, r5, r6, r7);
 
+	identify_ppc_sys_by_id(mfspr(SPRN_PVR));
+
 	ppc_md.setup_arch = ml300_setup_arch;
 	ppc_md.setup_io_mappings = ml300_map_io;
 	ppc_md.init_IRQ = ml300_init_irq;
diff --git a/arch/ppc/platforms/4xx/xilinx_ml300.h b/arch/ppc/platforms/4xx/xilinx_ml300.h
index f8c58841233..ae8bf1353b0 100644
--- a/arch/ppc/platforms/4xx/xilinx_ml300.h
+++ b/arch/ppc/platforms/4xx/xilinx_ml300.h
@@ -16,7 +16,7 @@
 #define __ASM_XILINX_ML300_H__
 
 /* ML300 has a Xilinx Virtex-II Pro processor */
-#include <platforms/4xx/virtex-ii_pro.h>
+#include <platforms/4xx/virtex.h>
 
 #ifndef __ASSEMBLY__
 
@@ -41,7 +41,7 @@ typedef struct board_info {
 #define PPC4xx_ONB_IO_VADDR	0u
 #define PPC4xx_ONB_IO_SIZE	0u
 
-#define PPC4xx_MACHINE_NAME "Xilinx ML300"
+#define PPC4xx_MACHINE_NAME "Xilinx ML300 Reference System"
 
 #endif /* __ASM_XILINX_ML300_H__ */
 #endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/xilinx_ml403.c b/arch/ppc/platforms/4xx/xilinx_ml403.c
new file mode 100644
index 00000000000..4c0c7e4c111
--- /dev/null
+++ b/arch/ppc/platforms/4xx/xilinx_ml403.c
@@ -0,0 +1,177 @@
+/*
+ * arch/ppc/platforms/4xx/xilinx_ml403.c
+ *
+ * Xilinx ML403 evaluation board initialization
+ *
+ * Author: Grant Likely <grant.likely@secretlab.ca>
+ *
+ * 2005 (c) Secret Lab Technologies Ltd.
+ * 2002-2004 (c) MontaVista Software, Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#include <linux/config.h>
+#include <linux/init.h>
+#include <linux/irq.h>
+#include <linux/tty.h>
+#include <linux/serial.h>
+#include <linux/serial_core.h>
+#include <linux/serial_8250.h>
+#include <linux/serialP.h>
+#include <asm/io.h>
+#include <asm/machdep.h>
+#include <asm/ppc_sys.h>
+
+#include <syslib/gen550.h>
+#include <platforms/4xx/xparameters/xparameters.h>
+
+/*
+ * As an overview of how the following functions (platform_init,
+ * ml403_map_io, ml403_setup_arch and ml403_init_IRQ) fit into the
+ * kernel startup procedure, here's a call tree:
+ *
+ * start_here					arch/ppc/kernel/head_4xx.S
+ *  early_init					arch/ppc/kernel/setup.c
+ *  machine_init				arch/ppc/kernel/setup.c
+ *    platform_init				this file
+ *      ppc4xx_init				arch/ppc/syslib/ppc4xx_setup.c
+ *        parse_bootinfo
+ *          find_bootinfo
+ *        "setup some default ppc_md pointers"
+ *  MMU_init					arch/ppc/mm/init.c
+ *    *ppc_md.setup_io_mappings == ml403_map_io	this file
+ *      ppc4xx_map_io				arch/ppc/syslib/ppc4xx_setup.c
+ *  start_kernel				init/main.c
+ *    setup_arch				arch/ppc/kernel/setup.c
+ * #if defined(CONFIG_KGDB)
+ *      *ppc_md.kgdb_map_scc() == gen550_kgdb_map_scc
+ * #endif
+ *      *ppc_md.setup_arch == ml403_setup_arch	this file
+ *        ppc4xx_setup_arch			arch/ppc/syslib/ppc4xx_setup.c
+ *          ppc4xx_find_bridges			arch/ppc/syslib/ppc405_pci.c
+ *    init_IRQ					arch/ppc/kernel/irq.c
+ *      *ppc_md.init_IRQ == ml403_init_IRQ	this file
+ *        ppc4xx_init_IRQ			arch/ppc/syslib/ppc4xx_setup.c
+ *          ppc4xx_pic_init			arch/ppc/syslib/xilinx_pic.c
+ */
+
+/* Board specifications structures */
+struct ppc_sys_spec *cur_ppc_sys_spec;
+struct ppc_sys_spec ppc_sys_specs[] = {
+	{
+		/* Only one entry, always assume the same design */
+		.ppc_sys_name	= "Xilinx ML403 Reference Design",
+		.mask 		= 0x00000000,
+		.value 		= 0x00000000,
+		.num_devices	= 1,
+		.device_list	= (enum ppc_sys_devices[])
+		{
+			VIRTEX_UART,
+		},
+	},
+};
+
+#if defined(XPAR_POWER_0_POWERDOWN_BASEADDR)
+
+static volatile unsigned *powerdown_base =
+    (volatile unsigned *) XPAR_POWER_0_POWERDOWN_BASEADDR;
+
+static void
+xilinx_power_off(void)
+{
+	local_irq_disable();
+	out_be32(powerdown_base, XPAR_POWER_0_POWERDOWN_VALUE);
+	while (1) ;
+}
+#endif
+
+void __init
+ml403_map_io(void)
+{
+	ppc4xx_map_io();
+
+#if defined(XPAR_POWER_0_POWERDOWN_BASEADDR)
+	powerdown_base = ioremap((unsigned long) powerdown_base,
+				 XPAR_POWER_0_POWERDOWN_HIGHADDR -
+				 XPAR_POWER_0_POWERDOWN_BASEADDR + 1);
+#endif
+}
+
+/* Early serial support functions */
+static void __init
+ml403_early_serial_init(int num, struct plat_serial8250_port *pdata)
+{
+#if defined(CONFIG_SERIAL_TEXT_DEBUG) || defined(CONFIG_KGDB)
+	struct uart_port serial_req;
+
+	memset(&serial_req, 0, sizeof(serial_req));
+	serial_req.mapbase	= pdata->mapbase;
+	serial_req.membase	= pdata->membase;
+	serial_req.irq		= pdata->irq;
+	serial_req.uartclk	= pdata->uartclk;
+	serial_req.regshift	= pdata->regshift;
+	serial_req.iotype	= pdata->iotype;
+	serial_req.flags	= pdata->flags;
+	gen550_init(num, &serial_req);
+#endif
+}
+
+void __init
+ml403_early_serial_map(void)
+{
+#ifdef CONFIG_SERIAL_8250
+	struct plat_serial8250_port *pdata;
+	int i = 0;
+
+	pdata = (struct plat_serial8250_port *) ppc_sys_get_pdata(VIRTEX_UART);
+	while(pdata && pdata->flags)
+	{
+		pdata->membase = ioremap(pdata->mapbase, 0x100);
+		ml403_early_serial_init(i, pdata);
+		pdata++;
+		i++;
+	}
+#endif /* CONFIG_SERIAL_8250 */
+}
+
+void __init
+ml403_setup_arch(void)
+{
+	ml403_early_serial_map();
+	ppc4xx_setup_arch();	/* calls ppc4xx_find_bridges() */
+
+	/* Identify the system */
+	printk(KERN_INFO "Xilinx ML403 Reference System (Virtex-4 FX)\n");
+}
+
+/* Called after board_setup_irq from ppc4xx_init_IRQ(). */
+void __init
+ml403_init_irq(void)
+{
+	ppc4xx_init_IRQ();
+}
+
+void __init
+platform_init(unsigned long r3, unsigned long r4, unsigned long r5,
+	      unsigned long r6, unsigned long r7)
+{
+	ppc4xx_init(r3, r4, r5, r6, r7);
+
+	identify_ppc_sys_by_id(mfspr(SPRN_PVR));
+
+	ppc_md.setup_arch = ml403_setup_arch;
+	ppc_md.setup_io_mappings = ml403_map_io;
+	ppc_md.init_IRQ = ml403_init_irq;
+
+#if defined(XPAR_POWER_0_POWERDOWN_BASEADDR)
+	ppc_md.power_off = xilinx_power_off;
+#endif
+
+#ifdef CONFIG_KGDB
+	ppc_md.early_serial_map = ml403_early_serial_map;
+#endif
+}
+
diff --git a/arch/ppc/platforms/4xx/xilinx_ml403.h b/arch/ppc/platforms/4xx/xilinx_ml403.h
new file mode 100644
index 00000000000..47359695990
--- /dev/null
+++ b/arch/ppc/platforms/4xx/xilinx_ml403.h
@@ -0,0 +1,49 @@
+/*
+ * arch/ppc/platforms/4xx/xilinx_ml403.h
+ *
+ * Include file that defines the Xilinx ML403 reference design
+ *
+ * Author: Grant Likely <grant.likely@secretlab.ca>
+ *
+ * 2005 (c) Secret Lab Technologies Ltd.
+ * 2002-2004 (c) MontaVista Software, Inc.
+ *
+ * This file is licensed under the terms of the GNU General Public License
+ * version 2.  This program is licensed "as is" without any warranty of any
+ * kind, whether express or implied.
+ */
+
+#ifdef __KERNEL__
+#ifndef __ASM_XILINX_ML403_H__
+#define __ASM_XILINX_ML403_H__
+
+/* ML403 has a Xilinx Virtex-4 FPGA with a PPC405 hard core */
+#include <platforms/4xx/virtex.h>
+
+#ifndef __ASSEMBLY__
+
+#include <linux/types.h>
+
+typedef struct board_info {
+	unsigned int	 bi_memsize;		/* DRAM installed, in bytes */
+	unsigned char	 bi_enetaddr[6];	/* Local Ethernet MAC address */
+	unsigned int	 bi_intfreq;		/* Processor speed, in Hz */
+	unsigned int	 bi_busfreq;		/* PLB Bus speed, in Hz */
+	unsigned int	 bi_pci_busfreq;	/* PCI Bus speed, in Hz */
+} bd_t;
+
+/* Some 4xx parts use a different timebase frequency from the internal clock.
+*/
+#define bi_tbfreq bi_intfreq
+
+#endif /* !__ASSEMBLY__ */
+
+/* We don't need anything mapped.  Size of zero will accomplish that. */
+#define PPC4xx_ONB_IO_PADDR	0u
+#define PPC4xx_ONB_IO_VADDR	0u
+#define PPC4xx_ONB_IO_SIZE	0u
+
+#define PPC4xx_MACHINE_NAME "Xilinx ML403 Reference Design"
+
+#endif /* __ASM_XILINX_ML403_H__ */
+#endif /* __KERNEL__ */
diff --git a/arch/ppc/platforms/4xx/xparameters/xparameters.h b/arch/ppc/platforms/4xx/xparameters/xparameters.h
new file mode 100644
index 00000000000..4cf21f25635
--- /dev/null
+++ b/arch/ppc/platforms/4xx/xparameters/xparameters.h
@@ -0,0 +1,37 @@
+/*
+ * include/asm-ppc/xparameters.h
+ *
+ * This file includes the correct xparameters.h for the CONFIG'ed board plus
+ * fixups to translate board specific XPAR values to a common set of names
+ *
+ * Author: MontaVista Software, Inc.
+ *         source@mvista.com
+ *
+ * 2004 (c) MontaVista Software, Inc.  This file is licensed under the terms
+ * of the GNU General Public License version 2.  This program is licensed
+ * "as is" without any warranty of any kind, whether express or implied.
+ */
+
+#include <linux/config.h>
+
+#if defined(CONFIG_XILINX_ML300)
+  #include "xparameters_ml300.h"
+#elif defined(CONFIG_XILINX_ML403)
+  #include "xparameters_ml403.h"
+#else
+  /* Add other board xparameter includes here before the #else */
+  #error No xparameters_*.h file included
+#endif
+
+#ifndef SERIAL_PORT_DFNS
+  /* zImage serial port definitions */
+  #define RS_TABLE_SIZE 1
+  #define SERIAL_PORT_DFNS {						\
+	.baud_base	 = XPAR_UARTNS550_0_CLOCK_FREQ_HZ/16,		\
+	.irq		 = XPAR_INTC_0_UARTNS550_0_VEC_ID,		\
+	.flags		 = ASYNC_BOOT_AUTOCONF,				\
+	.iomem_base	 = (u8 *)XPAR_UARTNS550_0_BASEADDR + 3,		\
+	.iomem_reg_shift = 2,						\
+	.io_type	 = SERIAL_IO_MEM,				\
+  },
+#endif
diff --git a/arch/ppc/platforms/4xx/xparameters/xparameters_ml403.h b/arch/ppc/platforms/4xx/xparameters/xparameters_ml403.h
new file mode 100644
index 00000000000..5cacdcb3964
--- /dev/null
+++ b/arch/ppc/platforms/4xx/xparameters/xparameters_ml403.h
@@ -0,0 +1,243 @@
+
+/*******************************************************************
+*
+* CAUTION: This file is automatically generated by libgen.
+* Version: Xilinx EDK 7.1.2 EDK_H.12.5.1
+* DO NOT EDIT.
+*
+* Copyright (c) 2005 Xilinx, Inc.  All rights reserved. 
+* 
+* Description: Driver parameters
+*
+*******************************************************************/
+
+#define XPAR_PLB_BRAM_IF_CNTLR_0_BASEADDR 0xFFFF0000
+#define XPAR_PLB_BRAM_IF_CNTLR_0_HIGHADDR 0xFFFFFFFF
+
+/******************************************************************/
+
+#define XPAR_OPB_EMC_0_MEM0_BASEADDR 0x20000000
+#define XPAR_OPB_EMC_0_MEM0_HIGHADDR 0x200FFFFF
+#define XPAR_OPB_EMC_0_MEM1_BASEADDR 0x28000000
+#define XPAR_OPB_EMC_0_MEM1_HIGHADDR 0x287FFFFF
+#define XPAR_OPB_AC97_CONTROLLER_REF_0_BASEADDR 0xA6000000
+#define XPAR_OPB_AC97_CONTROLLER_REF_0_HIGHADDR 0xA60000FF
+#define XPAR_OPB_EMC_USB_0_MEM0_BASEADDR 0xA5000000
+#define XPAR_OPB_EMC_USB_0_MEM0_HIGHADDR 0xA50000FF
+#define XPAR_PLB_DDR_0_MEM0_BASEADDR 0x00000000
+#define XPAR_PLB_DDR_0_MEM0_HIGHADDR 0x0FFFFFFF
+
+/******************************************************************/
+
+#define XPAR_XEMAC_NUM_INSTANCES 1
+#define XPAR_OPB_ETHERNET_0_BASEADDR 0x60000000
+#define XPAR_OPB_ETHERNET_0_HIGHADDR 0x60003FFF
+#define XPAR_OPB_ETHERNET_0_DEVICE_ID 0
+#define XPAR_OPB_ETHERNET_0_ERR_COUNT_EXIST 1
+#define XPAR_OPB_ETHERNET_0_DMA_PRESENT 1
+#define XPAR_OPB_ETHERNET_0_MII_EXIST 1
+
+/******************************************************************/
+
+#define XPAR_XUARTNS550_NUM_INSTANCES 1
+#define XPAR_XUARTNS550_CLOCK_HZ 100000000
+#define XPAR_OPB_UART16550_0_BASEADDR 0xA0000000
+#define XPAR_OPB_UART16550_0_HIGHADDR 0xA0001FFF
+#define XPAR_OPB_UART16550_0_DEVICE_ID 0
+
+/******************************************************************/
+
+#define XPAR_XGPIO_NUM_INSTANCES 3
+#define XPAR_OPB_GPIO_0_BASEADDR 0x90000000
+#define XPAR_OPB_GPIO_0_HIGHADDR 0x900001FF
+#define XPAR_OPB_GPIO_0_DEVICE_ID 0
+#define XPAR_OPB_GPIO_0_INTERRUPT_PRESENT 0
+#define XPAR_OPB_GPIO_0_IS_DUAL 1
+#define XPAR_OPB_GPIO_EXP_HDR_0_BASEADDR 0x90001000
+#define XPAR_OPB_GPIO_EXP_HDR_0_HIGHADDR 0x900011FF
+#define XPAR_OPB_GPIO_EXP_HDR_0_DEVICE_ID 1
+#define XPAR_OPB_GPIO_EXP_HDR_0_INTERRUPT_PRESENT 0
+#define XPAR_OPB_GPIO_EXP_HDR_0_IS_DUAL 1
+#define XPAR_OPB_GPIO_CHAR_LCD_0_BASEADDR 0x90002000
+#define XPAR_OPB_GPIO_CHAR_LCD_0_HIGHADDR 0x900021FF
+#define XPAR_OPB_GPIO_CHAR_LCD_0_DEVICE_ID 2
+#define XPAR_OPB_GPIO_CHAR_LCD_0_INTERRUPT_PRESENT 0
+#define XPAR_OPB_GPIO_CHAR_LCD_0_IS_DUAL 0
+
+/******************************************************************/
+
+#define XPAR_XPS2_NUM_INSTANCES 2
+#define XPAR_OPB_PS2_DUAL_REF_0_DEVICE_ID_0 0
+#define XPAR_OPB_PS2_DUAL_REF_0_BASEADDR_0 0xA9000000
+#define XPAR_OPB_PS2_DUAL_REF_0_HIGHADDR_0 (0xA9000000+0x3F)
+#define XPAR_OPB_PS2_DUAL_REF_0_DEVICE_ID_1 1
+#define XPAR_OPB_PS2_DUAL_REF_0_BASEADDR_1 (0xA9000000+0x1000)
+#define XPAR_OPB_PS2_DUAL_REF_0_HIGHADDR_1 (0xA9000000+0x103F)
+
+/******************************************************************/
+
+#define XPAR_XIIC_NUM_INSTANCES 1
+#define XPAR_OPB_IIC_0_BASEADDR 0xA8000000
+#define XPAR_OPB_IIC_0_HIGHADDR 0xA80001FF
+#define XPAR_OPB_IIC_0_DEVICE_ID 0
+#define XPAR_OPB_IIC_0_TEN_BIT_ADR 0
+#define XPAR_OPB_IIC_0_GPO_WIDTH 1
+
+/******************************************************************/
+
+#define XPAR_INTC_MAX_NUM_INTR_INPUTS 10
+#define XPAR_XINTC_HAS_IPR 1
+#define XPAR_XINTC_USE_DCR 0
+#define XPAR_XINTC_NUM_INSTANCES 1
+#define XPAR_OPB_INTC_0_BASEADDR 0xD1000FC0
+#define XPAR_OPB_INTC_0_HIGHADDR 0xD1000FDF
+#define XPAR_OPB_INTC_0_DEVICE_ID 0
+#define XPAR_OPB_INTC_0_KIND_OF_INTR 0x00000000
+
+/******************************************************************/
+
+#define XPAR_INTC_SINGLE_BASEADDR 0xD1000FC0
+#define XPAR_INTC_SINGLE_HIGHADDR 0xD1000FDF
+#define XPAR_INTC_SINGLE_DEVICE_ID XPAR_OPB_INTC_0_DEVICE_ID
+#define XPAR_OPB_ETHERNET_0_IP2INTC_IRPT_MASK 0X000001
+#define XPAR_OPB_INTC_0_OPB_ETHERNET_0_IP2INTC_IRPT_INTR 0
+#define XPAR_SYSTEM_USB_HPI_INT_MASK 0X000002
+#define XPAR_OPB_INTC_0_SYSTEM_USB_HPI_INT_INTR 1
+#define XPAR_MISC_LOGIC_0_PHY_MII_INT_MASK 0X000004
+#define XPAR_OPB_INTC_0_MISC_LOGIC_0_PHY_MII_INT_INTR 2
+#define XPAR_OPB_SYSACE_0_SYSACE_IRQ_MASK 0X000008
+#define XPAR_OPB_INTC_0_OPB_SYSACE_0_SYSACE_IRQ_INTR 3
+#define XPAR_OPB_AC97_CONTROLLER_REF_0_RECORD_INTERRUPT_MASK 0X000010
+#define XPAR_OPB_INTC_0_OPB_AC97_CONTROLLER_REF_0_RECORD_INTERRUPT_INTR 4
+#define XPAR_OPB_AC97_CONTROLLER_REF_0_PLAYBACK_INTERRUPT_MASK 0X000020
+#define XPAR_OPB_INTC_0_OPB_AC97_CONTROLLER_REF_0_PLAYBACK_INTERRUPT_INTR 5
+#define XPAR_OPB_IIC_0_IP2INTC_IRPT_MASK 0X000040
+#define XPAR_OPB_INTC_0_OPB_IIC_0_IP2INTC_IRPT_INTR 6
+#define XPAR_OPB_PS2_DUAL_REF_0_SYS_INTR2_MASK 0X000080
+#define XPAR_OPB_INTC_0_OPB_PS2_DUAL_REF_0_SYS_INTR2_INTR 7
+#define XPAR_OPB_PS2_DUAL_REF_0_SYS_INTR1_MASK 0X000100
+#define XPAR_OPB_INTC_0_OPB_PS2_DUAL_REF_0_SYS_INTR1_INTR 8
+#define XPAR_OPB_UART16550_0_IP2INTC_IRPT_MASK 0X000200
+#define XPAR_OPB_INTC_0_OPB_UART16550_0_IP2INTC_IRPT_INTR 9
+
+/******************************************************************/
+
+#define XPAR_XTFT_NUM_INSTANCES 1
+#define XPAR_PLB_TFT_CNTLR_REF_0_DCR_BASEADDR 0xD0000200
+#define XPAR_PLB_TFT_CNTLR_REF_0_DCR_HIGHADDR 0xD0000207
+#define XPAR_PLB_TFT_CNTLR_REF_0_DEVICE_ID 0
+
+/******************************************************************/
+
+#define XPAR_XSYSACE_MEM_WIDTH 16
+#define XPAR_XSYSACE_NUM_INSTANCES 1
+#define XPAR_OPB_SYSACE_0_BASEADDR 0xCF000000
+#define XPAR_OPB_SYSACE_0_HIGHADDR 0xCF0001FF
+#define XPAR_OPB_SYSACE_0_DEVICE_ID 0
+#define XPAR_OPB_SYSACE_0_MEM_WIDTH 16
+
+/******************************************************************/
+
+#define XPAR_CPU_PPC405_CORE_CLOCK_FREQ_HZ 300000000
+
+/******************************************************************/
+
+
+/******************************************************************/
+
+/* Linux Redefines */
+
+/******************************************************************/
+
+#define XPAR_UARTNS550_0_BASEADDR (XPAR_OPB_UART16550_0_BASEADDR+0x1000)
+#define XPAR_UARTNS550_0_HIGHADDR XPAR_OPB_UART16550_0_HIGHADDR
+#define XPAR_UARTNS550_0_CLOCK_FREQ_HZ XPAR_XUARTNS550_CLOCK_HZ
+#define XPAR_UARTNS550_0_DEVICE_ID XPAR_OPB_UART16550_0_DEVICE_ID
+
+/******************************************************************/
+
+#define XPAR_INTC_0_BASEADDR XPAR_OPB_INTC_0_BASEADDR
+#define XPAR_INTC_0_HIGHADDR XPAR_OPB_INTC_0_HIGHADDR
+#define XPAR_INTC_0_KIND_OF_INTR XPAR_OPB_INTC_0_KIND_OF_INTR
+#define XPAR_INTC_0_DEVICE_ID XPAR_OPB_INTC_0_DEVICE_ID
+
+/******************************************************************/
+
+#define XPAR_INTC_0_EMAC_0_VEC_ID XPAR_OPB_INTC_0_OPB_ETHERNET_0_IP2INTC_IRPT_INTR
+#define XPAR_INTC_0_SYSACE_0_VEC_ID XPAR_OPB_INTC_0_OPB_SYSACE_0_SYSACE_IRQ_INTR
+#define XPAR_INTC_0_IIC_0_VEC_ID XPAR_OPB_INTC_0_OPB_IIC_0_IP2INTC_IRPT_INTR
+#define XPAR_INTC_0_PS2_1_VEC_ID XPAR_OPB_INTC_0_OPB_PS2_DUAL_REF_0_SYS_INTR2_INTR
+#define XPAR_INTC_0_PS2_0_VEC_ID XPAR_OPB_INTC_0_OPB_PS2_DUAL_REF_0_SYS_INTR1_INTR
+#define XPAR_INTC_0_UARTNS550_0_VEC_ID XPAR_OPB_INTC_0_OPB_UART16550_0_IP2INTC_IRPT_INTR
+
+/******************************************************************/
+
+#define XPAR_TFT_0_BASEADDR XPAR_PLB_TFT_CNTLR_REF_0_DCR_BASEADDR
+
+/******************************************************************/
+
+#define XPAR_EMAC_0_BASEADDR XPAR_OPB_ETHERNET_0_BASEADDR
+#define XPAR_EMAC_0_HIGHADDR XPAR_OPB_ETHERNET_0_HIGHADDR
+#define XPAR_EMAC_0_DMA_PRESENT XPAR_OPB_ETHERNET_0_DMA_PRESENT
+#define XPAR_EMAC_0_MII_EXIST XPAR_OPB_ETHERNET_0_MII_EXIST
+#define XPAR_EMAC_0_ERR_COUNT_EXIST XPAR_OPB_ETHERNET_0_ERR_COUNT_EXIST
+#define XPAR_EMAC_0_DEVICE_ID XPAR_OPB_ETHERNET_0_DEVICE_ID
+
+/******************************************************************/
+
+#define XPAR_GPIO_0_BASEADDR XPAR_OPB_GPIO_0_BASEADDR_0
+#define XPAR_GPIO_0_HIGHADDR XPAR_OPB_GPIO_0_HIGHADDR_0
+#define XPAR_GPIO_0_DEVICE_ID XPAR_OPB_GPIO_0_DEVICE_ID_0
+#define XPAR_GPIO_1_BASEADDR XPAR_OPB_GPIO_0_BASEADDR_1
+#define XPAR_GPIO_1_HIGHADDR XPAR_OPB_GPIO_0_HIGHADDR_1
+#define XPAR_GPIO_1_DEVICE_ID XPAR_OPB_GPIO_0_DEVICE_ID_1
+#define XPAR_GPIO_2_BASEADDR XPAR_OPB_GPIO_EXP_HDR_0_BASEADDR_0
+#define XPAR_GPIO_2_HIGHADDR XPAR_OPB_GPIO_EXP_HDR_0_HIGHADDR_0
+#define XPAR_GPIO_2_DEVICE_ID XPAR_OPB_GPIO_EXP_HDR_0_DEVICE_ID_0
+#define XPAR_GPIO_3_BASEADDR XPAR_OPB_GPIO_EXP_HDR_0_BASEADDR_1
+#define XPAR_GPIO_3_HIGHADDR XPAR_OPB_GPIO_EXP_HDR_0_HIGHADDR_1
+#define XPAR_GPIO_3_DEVICE_ID XPAR_OPB_GPIO_EXP_HDR_0_DEVICE_ID_1
+#define XPAR_GPIO_4_BASEADDR XPAR_OPB_GPIO_CHAR_LCD_0_BASEADDR
+#define XPAR_GPIO_4_HIGHADDR XPAR_OPB_GPIO_CHAR_LCD_0_HIGHADDR
+#define XPAR_GPIO_4_DEVICE_ID XPAR_OPB_GPIO_CHAR_LCD_0_DEVICE_ID
+
+/******************************************************************/
+
+#define XPAR_PS2_0_BASEADDR XPAR_OPB_PS2_DUAL_REF_0_BASEADDR_0
+#define XPAR_PS2_0_HIGHADDR XPAR_OPB_PS2_DUAL_REF_0_HIGHADDR_0
+#define XPAR_PS2_0_DEVICE_ID XPAR_OPB_PS2_DUAL_REF_0_DEVICE_ID_0
+#define XPAR_PS2_1_BASEADDR XPAR_OPB_PS2_DUAL_REF_0_BASEADDR_1
+#define XPAR_PS2_1_HIGHADDR XPAR_OPB_PS2_DUAL_REF_0_HIGHADDR_1
+#define XPAR_PS2_1_DEVICE_ID XPAR_OPB_PS2_DUAL_REF_0_DEVICE_ID_1
+
+/******************************************************************/
+
+#define XPAR_SYSACE_0_BASEADDR XPAR_OPB_SYSACE_0_BASEADDR
+#define XPAR_SYSACE_0_HIGHADDR XPAR_OPB_SYSACE_0_HIGHADDR
+#define XPAR_SYSACE_0_DEVICE_ID XPAR_OPB_SYSACE_0_DEVICE_ID
+
+/******************************************************************/
+
+#define XPAR_IIC_0_BASEADDR XPAR_OPB_IIC_0_BASEADDR
+#define XPAR_IIC_0_HIGHADDR XPAR_OPB_IIC_0_HIGHADDR
+#define XPAR_IIC_0_TEN_BIT_ADR XPAR_OPB_IIC_0_TEN_BIT_ADR
+#define XPAR_IIC_0_DEVICE_ID XPAR_OPB_IIC_0_DEVICE_ID
+
+/******************************************************************/
+
+#define XPAR_PLB_CLOCK_FREQ_HZ 100000000
+#define XPAR_CORE_CLOCK_FREQ_HZ XPAR_CPU_PPC405_CORE_CLOCK_FREQ_HZ
+#define XPAR_DDR_0_SIZE 0x4000000
+
+/******************************************************************/
+
+#define XPAR_PERSISTENT_0_IIC_0_BASEADDR 0x00000400
+#define XPAR_PERSISTENT_0_IIC_0_HIGHADDR 0x000007FF
+#define XPAR_PERSISTENT_0_IIC_0_EEPROMADDR 0xA0
+
+/******************************************************************/
+
+#define XPAR_PCI_0_CLOCK_FREQ_HZ    0
+
+/******************************************************************/
+