diff options
| author | Chen Liqin <liqin.chen@sunplusct.com> | 2009-08-30 10:26:23 +0800 |
|---|---|---|
| committer | Chen Liqin <liqin.chen@sunplusct.com> | 2009-08-30 10:26:23 +0800 |
| commit | d27eadc7612404b06f99888c02726ab7d5036e0f (patch) | |
| tree | ed32b38e1cd4cbc52506c27c8cc353161255c9d6 /arch/score/include/asm/scoreregs.h | |
| parent | adda766193ea1cf3137484a9521972d080d0b7af (diff) | |
| parent | fbd85b0e26bab0a13dcf860f2c20e86cb0507b61 (diff) | |
Merge branch 'score' of git://git.kernel.org/pub/scm/linux/kernel/git/arnd/asm-generic into for-linus
* 'score' of git://git.kernel.org/pub/scm/linux/kernel/git/arnd/asm-generic:
score: clean up mm/init.c
score: make irq.h definitions local
score: cleanups: dead code, 0 as pointer, shadowed variables
score: fix function prototypes
score: add address space annotations
score: add missing #includes
score: move save arg5 and arg6 instruction in front of enable_irq
score: add prototypes for wrapped syscalls
score: remove init_mm
score: add generic sys_call_table
score: remove __{put,get}_user_unknown
score: unset __ARCH_WANT_IPC_PARSE_VERSION
score: update files according to review comments
score: add maintainers for score architecture
score: Add support for Sunplus S+core architecture
Diffstat (limited to 'arch/score/include/asm/scoreregs.h')
| -rw-r--r-- | arch/score/include/asm/scoreregs.h | 51 |
1 files changed, 51 insertions, 0 deletions
diff --git a/arch/score/include/asm/scoreregs.h b/arch/score/include/asm/scoreregs.h new file mode 100644 index 00000000000..d0ad2920451 --- /dev/null +++ b/arch/score/include/asm/scoreregs.h @@ -0,0 +1,51 @@ +#ifndef _ASM_SCORE_SCOREREGS_H +#define _ASM_SCORE_SCOREREGS_H + +#include <linux/linkage.h> + +/* TIMER register */ +#define TIME0BASE 0x96080000 +#define P_TIMER0_CTRL (TIME0BASE + 0x00) +#define P_TIMER0_CPP_CTRL (TIME0BASE + 0x04) +#define P_TIMER0_PRELOAD (TIME0BASE + 0x08) +#define P_TIMER0_CPP_REG (TIME0BASE + 0x0C) +#define P_TIMER0_UPCNT (TIME0BASE + 0x10) + +/* Timer Controller Register */ +/* bit 0 Timer enable */ +#define TMR_DISABLE 0x0000 +#define TMR_ENABLE 0x0001 + +/* bit 1 Interrupt enable */ +#define TMR_IE_DISABLE 0x0000 +#define TMR_IE_ENABLE 0x0002 + +/* bit 2 Output enable */ +#define TMR_OE_DISABLE 0x0004 +#define TMR_OE_ENABLE 0x0000 + +/* bit4 Up/Down counting selection */ +#define TMR_UD_DOWN 0x0000 +#define TMR_UD_UP 0x0010 + +/* bit5 Up/Down counting control selection */ +#define TMR_UDS_UD 0x0000 +#define TMR_UDS_EXTUD 0x0020 + +/* bit6 Time output mode */ +#define TMR_OM_TOGGLE 0x0000 +#define TMR_OM_PILSE 0x0040 + +/* bit 8..9 External input active edge selection */ +#define TMR_ES_PE 0x0000 +#define TMR_ES_NE 0x0100 +#define TMR_ES_BOTH 0x0200 + +/* bit 10..11 Operating mode */ +#define TMR_M_FREE 0x0000 /* free running timer mode */ +#define TMR_M_PERIODIC 0x0400 /* periodic timer mode */ +#define TMR_M_FC 0x0800 /* free running counter mode */ +#define TMR_M_PC 0x0c00 /* periodic counter mode */ + +#define SYSTEM_CLOCK (27*1000000/4) /* 27 MHz */ +#endif /* _ASM_SCORE_SCOREREGS_H */ |