diff options
| author | Nobuhiro Iwamatsu <iwamatsu@nigauri.org> | 2007-03-26 14:27:43 +0900 |
|---|---|---|
| committer | Paul Mundt <lethal@hera.kernel.org> | 2007-05-07 02:10:54 +0000 |
| commit | c86c5a910451dd5a30e62a9e36d8e9b3c7a0c1d1 (patch) | |
| tree | 69acbb65e61a8895dfdebfd70dc58f5d8d9dbe38 /arch/sh/drivers/pci/fixups-lboxre2.c | |
| parent | 00e8c494a1603eac0a2cae9836e624a752ad45b1 (diff) | |
sh: L-BOX RE2 support.
This adds support for the L-BOX RE2 router.
http://www.nttcom.co.jp/l-box/
L-BOX RE2 is a SH7751R-based router. It has CF, Cardbus, serial,
and LAN x2. This is one of the very few SH boards that a general
person can obtain now.
The L-BOX shipped with a 2.4.28 kernel, this is a rewritten patch
adding it to current git.
Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/drivers/pci/fixups-lboxre2.c')
| -rw-r--r-- | arch/sh/drivers/pci/fixups-lboxre2.c | 41 |
1 files changed, 41 insertions, 0 deletions
diff --git a/arch/sh/drivers/pci/fixups-lboxre2.c b/arch/sh/drivers/pci/fixups-lboxre2.c new file mode 100644 index 00000000000..40b19bdfb89 --- /dev/null +++ b/arch/sh/drivers/pci/fixups-lboxre2.c @@ -0,0 +1,41 @@ +/* + * arch/sh/drivers/pci/fixups-lboxre2.c + * + * L-BOX RE2 PCI fixups + * + * Copyright (C) 2007 Nobuhiro Iwamatsu + * + * This file is subject to the terms and conditions of the GNU General Public + * License. See the file "COPYING" in the main directory of this archive + * for more details. + */ +#include "pci-sh4.h" + +#define PCIMCR_MRSET_OFF 0xBFFFFFFF +#define PCIMCR_RFSH_OFF 0xFFFFFFFB + +int pci_fixup_pcic(void) +{ + unsigned long bcr1, mcr; + + bcr1 = inl(SH7751_BCR1); + bcr1 |= 0x40080000; /* Enable Bit 19 BREQEN, set PCIC to slave */ + pci_write_reg(bcr1, SH4_PCIBCR1); + + /* Enable all interrupts, so we known what to fix */ + pci_write_reg(0x0000c3ff, SH4_PCIINTM); + pci_write_reg(0x0000380f, SH4_PCIAINTM); + pci_write_reg(0xfb900047, SH7751_PCICONF1); + pci_write_reg(0xab000001, SH7751_PCICONF4); + + mcr = inl(SH7751_MCR); + mcr = (mcr & PCIMCR_MRSET_OFF) & PCIMCR_RFSH_OFF; + pci_write_reg(mcr, SH4_PCIMCR); + + pci_write_reg(0x0c000000, SH7751_PCICONF5); + pci_write_reg(0xd0000000, SH7751_PCICONF6); + pci_write_reg(0x0c000000, SH4_PCILAR0); + pci_write_reg(0x00000000, SH4_PCILAR1); + + return 0; +} |