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authorPaul Mundt <lethal@linux-sh.org>2010-03-04 16:44:20 +0900
committerPaul Mundt <lethal@linux-sh.org>2010-03-04 16:44:20 +0900
commit281983d6ff2674ca2e4868de628c65809d84fa4c (patch)
treeabdf15ec83c5086220aff0c92d2112f8e05c3041 /arch/sh/include/asm/cacheflush.h
parent09e1172317d1038918c5a139ba31155610f802b5 (diff)
sh: fix up MMU reset with variable PMB mapping sizes.
Presently we run in to issues with the MMU resetting the CPU when variable sized mappings are employed. This takes a slightly more aggressive approach to keeping the TLB and cache state sane before establishing the mappings in order to cut down on races observed on SMP configurations. At the same time, we bump the VMA range up to the 0xb000...0xc000 range, as there still seems to be some undocumented behaviour in setting up variable mappings in the 0xa000...0xb000 range, resulting in reset by the TLB. Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/include/asm/cacheflush.h')
0 files changed, 0 insertions, 0 deletions