diff options
| author | Yoshinori Sato <ysato@users.sourceforge.jp> | 2008-08-04 16:33:47 +0900 |
|---|---|---|
| committer | Paul Mundt <lethal@linux-sh.org> | 2008-08-04 16:33:47 +0900 |
| commit | cce2d453e4940d3fccd42a6917d01027148e11c3 (patch) | |
| tree | bf921bfd41e4a40e513a1994d474e03f44089c0e /arch/sh/include/cpu-sh2a | |
| parent | 1af446edfe3239b2b731f3458b3c285c397464cc (diff) | |
SH2(A) cache update
Includes:
- SH2 (7619) Writeback support.
- SH2A cache handling fix.
Signed-off-by: Yoshinori Sato <ysato@users.sourceforge.jp>
Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/include/cpu-sh2a')
| -rw-r--r-- | arch/sh/include/cpu-sh2a/cpu/cache.h | 3 | ||||
| -rw-r--r-- | arch/sh/include/cpu-sh2a/cpu/cacheflush.h | 34 |
2 files changed, 37 insertions, 0 deletions
diff --git a/arch/sh/include/cpu-sh2a/cpu/cache.h b/arch/sh/include/cpu-sh2a/cpu/cache.h index afe228b3f49..defb0baa5a0 100644 --- a/arch/sh/include/cpu-sh2a/cpu/cache.h +++ b/arch/sh/include/cpu-sh2a/cpu/cache.h @@ -36,5 +36,8 @@ #define CCR_CACHE_ENABLE (CCR_CACHE_OCE | CCR_CACHE_ICE) #define CCR_CACHE_INVALIDATE (CCR_CACHE_OCI | CCR_CACHE_ICI) +#define CCR_ICACHE_INVALIDATE CCR_CACHE_ICI +#define CCR_OCACHE_INVALIDATE CCR_CACHE_OCI +#define CACHE_PHYSADDR_MASK 0x1ffffc00 #endif /* __ASM_CPU_SH2A_CACHE_H */ diff --git a/arch/sh/include/cpu-sh2a/cpu/cacheflush.h b/arch/sh/include/cpu-sh2a/cpu/cacheflush.h new file mode 100644 index 00000000000..3d3b9205d2a --- /dev/null +++ b/arch/sh/include/cpu-sh2a/cpu/cacheflush.h @@ -0,0 +1,34 @@ +#ifndef __ASM_CPU_SH2A_CACHEFLUSH_H +#define __ASM_CPU_SH2A_CACHEFLUSH_H + +/* + * Cache flushing: + * + * - flush_cache_all() flushes entire cache + * - flush_cache_mm(mm) flushes the specified mm context's cache lines + * - flush_cache_dup mm(mm) handles cache flushing when forking + * - flush_cache_page(mm, vmaddr, pfn) flushes a single page + * - flush_cache_range(vma, start, end) flushes a range of pages + * + * - flush_dcache_page(pg) flushes(wback&invalidates) a page for dcache + * - flush_icache_range(start, end) flushes(invalidates) a range for icache + * - flush_icache_page(vma, pg) flushes(invalidates) a page for icache + * + * Caches are indexed (effectively) by physical address on SH-2, so + * we don't need them. + */ +#define flush_cache_all() do { } while (0) +#define flush_cache_mm(mm) do { } while (0) +#define flush_cache_dup_mm(mm) do { } while (0) +#define flush_cache_range(vma, start, end) do { } while (0) +#define flush_cache_page(vma, vmaddr, pfn) do { } while (0) +#define flush_dcache_page(page) do { } while (0) +#define flush_dcache_mmap_lock(mapping) do { } while (0) +#define flush_dcache_mmap_unlock(mapping) do { } while (0) +void flush_icache_range(unsigned long start, unsigned long end); +#define flush_icache_page(vma,pg) do { } while (0) +#define flush_icache_user_range(vma,pg,adr,len) do { } while (0) +#define flush_cache_sigtramp(vaddr) do { } while (0) + +#define p3_cache_init() do { } while (0) +#endif /* __ASM_CPU_SH2A_CACHEFLUSH_H */ |