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authorKuninori Morimoto <morimoto.kuninori@renesas.com>2009-03-03 15:40:25 +0900
committerPaul Mundt <lethal@linux-sh.org>2009-03-03 15:40:25 +0900
commit55ba99eb211a06709237cb322ecd8c8b6faf6159 (patch)
treedc22ab87110e3e8fd26496fe6eebfbf261cc6c62 /arch/sh/include
parent93fde774546c947ac8563da431f0a6d47452551d (diff)
sh: Add support for SH7786 CPU subtype.
This adds preliminary support for the SH7786 CPU subtype. While this is a dual-core CPU, only UP is supported for now. L2 cache support is likewise not yet implemented. More information on this particular CPU subtype is available at: http://www.renesas.com/fmwk.jsp?cnt=sh7786_root.jsp&fp=/products/mpumcu/superh_family/sh7780_series/sh7786_group/ Signed-off-by: Kuninori Morimoto <morimoto.kuninori@renesas.com> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
Diffstat (limited to 'arch/sh/include')
-rw-r--r--arch/sh/include/asm/processor.h2
-rw-r--r--arch/sh/include/cpu-sh4/cpu/freq.h4
-rw-r--r--arch/sh/include/cpu-sh4/cpu/sh7786.h192
3 files changed, 197 insertions, 1 deletions
diff --git a/arch/sh/include/asm/processor.h b/arch/sh/include/asm/processor.h
index 1ef4b24d761..1fd58b42143 100644
--- a/arch/sh/include/asm/processor.h
+++ b/arch/sh/include/asm/processor.h
@@ -31,7 +31,7 @@ enum cpu_type {
CPU_SH7760, CPU_SH4_202, CPU_SH4_501,
/* SH-4A types */
- CPU_SH7763, CPU_SH7770, CPU_SH7780, CPU_SH7781, CPU_SH7785,
+ CPU_SH7763, CPU_SH7770, CPU_SH7780, CPU_SH7781, CPU_SH7785, CPU_SH7786,
CPU_SH7723, CPU_SHX3,
/* SH4AL-DSP types */
diff --git a/arch/sh/include/cpu-sh4/cpu/freq.h b/arch/sh/include/cpu-sh4/cpu/freq.h
index c23af81c2e7..749d1c43433 100644
--- a/arch/sh/include/cpu-sh4/cpu/freq.h
+++ b/arch/sh/include/cpu-sh4/cpu/freq.h
@@ -29,6 +29,10 @@
#define FRQCR0 0xffc80000
#define FRQCR1 0xffc80004
#define FRQMR1 0xffc80014
+#elif defined(CONFIG_CPU_SUBTYPE_SH7786)
+#define FRQCR0 0xffc40000
+#define FRQCR1 0xffc40004
+#define FRQMR1 0xffc40014
#elif defined(CONFIG_CPU_SUBTYPE_SHX3)
#define FRQCR 0xffc00014
#else
diff --git a/arch/sh/include/cpu-sh4/cpu/sh7786.h b/arch/sh/include/cpu-sh4/cpu/sh7786.h
new file mode 100644
index 00000000000..48688adc0c8
--- /dev/null
+++ b/arch/sh/include/cpu-sh4/cpu/sh7786.h
@@ -0,0 +1,192 @@
+/*
+ * SH7786 Pinmux
+ *
+ * Copyright (C) 2008, 2009 Renesas Solutions Corp.
+ * Kuninori Morimoto <morimoto.kuninori@renesas.com>
+ *
+ * Based on sh7785.h
+ *
+ * This file is subject to the terms and conditions of the GNU General Public
+ * License. See the file "COPYING" in the main directory of this archive
+ * for more details.
+ */
+
+#ifndef __CPU_SH7786_H__
+#define __CPU_SH7786_H__
+
+enum {
+ /* PA */
+ GPIO_PA7, GPIO_PA6, GPIO_PA5, GPIO_PA4,
+ GPIO_PA3, GPIO_PA2, GPIO_PA1, GPIO_PA0,
+
+ /* PB */
+ GPIO_PB7, GPIO_PB6, GPIO_PB5, GPIO_PB4,
+ GPIO_PB3, GPIO_PB2, GPIO_PB1, GPIO_PB0,
+
+ /* PC */
+ GPIO_PC7, GPIO_PC6, GPIO_PC5, GPIO_PC4,
+ GPIO_PC3, GPIO_PC2, GPIO_PC1, GPIO_PC0,
+
+ /* PD */
+ GPIO_PD7, GPIO_PD6, GPIO_PD5, GPIO_PD4,
+ GPIO_PD3, GPIO_PD2, GPIO_PD1, GPIO_PD0,
+
+ /* PE */
+ GPIO_PE5, GPIO_PE4, GPIO_PE3, GPIO_PE2,
+ GPIO_PE1, GPIO_PE0,
+
+ /* PF */
+ GPIO_PF7, GPIO_PF6, GPIO_PF5, GPIO_PF4,
+ GPIO_PF3, GPIO_PF2, GPIO_PF1, GPIO_PF0,
+
+ /* PG */
+ GPIO_PG7, GPIO_PG6, GPIO_PG5, GPIO_PG4,
+ GPIO_PG3, GPIO_PG2, GPIO_PG1, GPIO_PG0,
+
+ /* PH */
+ GPIO_PH7, GPIO_PH6, GPIO_PH5, GPIO_PH4,
+ GPIO_PH3, GPIO_PH2, GPIO_PH1, GPIO_PH0,
+
+ /* PJ */
+ GPIO_PJ7, GPIO_PJ6, GPIO_PJ5, GPIO_PJ4,
+ GPIO_PJ3, GPIO_PJ2, GPIO_PJ1, GPIO_PJ0,
+
+ GPIO_FN_CDE,
+ GPIO_FN_ETH_MAGIC,
+ GPIO_FN_DISP,
+ GPIO_FN_ETH_LINK,
+ GPIO_FN_DR5,
+ GPIO_FN_ETH_TX_ER,
+ GPIO_FN_DR4,
+ GPIO_FN_ETH_TX_EN,
+ GPIO_FN_DR3,
+ GPIO_FN_ETH_TXD3,
+ GPIO_FN_DR2,
+ GPIO_FN_ETH_TXD2,
+ GPIO_FN_DR1,
+ GPIO_FN_ETH_TXD1,
+ GPIO_FN_DR0,
+ GPIO_FN_ETH_TXD0,
+ GPIO_FN_VSYNC,
+ GPIO_FN_HSPI_CLK,
+ GPIO_FN_ODDF,
+ GPIO_FN_HSPI_CS,
+ GPIO_FN_DG5,
+ GPIO_FN_ETH_MDIO,
+ GPIO_FN_DG4,
+ GPIO_FN_ETH_RX_CLK,
+ GPIO_FN_DG3,
+ GPIO_FN_ETH_MDC,
+ GPIO_FN_DG2,
+ GPIO_FN_ETH_COL,
+ GPIO_FN_DG1,
+ GPIO_FN_ETH_TX_CLK,
+ GPIO_FN_DG0,
+ GPIO_FN_ETH_CRS,
+ GPIO_FN_DCLKIN,
+ GPIO_FN_HSPI_RX,
+ GPIO_FN_HSYNC,
+ GPIO_FN_HSPI_TX,
+ GPIO_FN_DB5,
+ GPIO_FN_ETH_RXD3,
+ GPIO_FN_DB4,
+ GPIO_FN_ETH_RXD2,
+ GPIO_FN_DB3,
+ GPIO_FN_ETH_RXD1,
+ GPIO_FN_DB2,
+ GPIO_FN_ETH_RXD0,
+ GPIO_FN_DB1,
+ GPIO_FN_ETH_RX_DV,
+ GPIO_FN_DB0,
+ GPIO_FN_ETH_RX_ER,
+ GPIO_FN_DCLKOUT,
+ GPIO_FN_SCIF1_SLK,
+ GPIO_FN_SCIF1_RXD,
+ GPIO_FN_SCIF1_TXD,
+ GPIO_FN_DACK1,
+ GPIO_FN_BACK,
+ GPIO_FN_FALE,
+ GPIO_FN_DACK0,
+ GPIO_FN_FCLE,
+ GPIO_FN_DREQ1,
+ GPIO_FN_BREQ,
+ GPIO_FN_USB_OVC1,
+ GPIO_FN_DREQ0,
+ GPIO_FN_USB_OVC0,
+ GPIO_FN_USB_PENC1,
+ GPIO_FN_USB_PENC0,
+ GPIO_FN_HAC1_SDOUT,
+ GPIO_FN_SSI1_SDATA,
+ GPIO_FN_SDIF1CMD,
+ GPIO_FN_HAC1_SDIN,
+ GPIO_FN_SSI1_SCK,
+ GPIO_FN_SDIF1CD,
+ GPIO_FN_HAC1_SYNC,
+ GPIO_FN_SSI1_WS,
+ GPIO_FN_SDIF1WP,
+ GPIO_FN_HAC1_BITCLK,
+ GPIO_FN_SSI1_CLK,
+ GPIO_FN_SDIF1CLK,
+ GPIO_FN_HAC0_SDOUT,
+ GPIO_FN_SSI0_SDATA,
+ GPIO_FN_SDIF1D3,
+ GPIO_FN_HAC0_SDIN,
+ GPIO_FN_SSI0_SCK,
+ GPIO_FN_SDIF1D2,
+ GPIO_FN_HAC0_SYNC,
+ GPIO_FN_SSI0_WS,
+ GPIO_FN_SDIF1D1,
+ GPIO_FN_HAC0_BITCLK,
+ GPIO_FN_SSI0_CLK,
+ GPIO_FN_SDIF1D0,
+ GPIO_FN_SCIF3_SCK,
+ GPIO_FN_SSI2_SDATA,
+ GPIO_FN_SCIF3_RXD,
+ GPIO_FN_TCLK,
+ GPIO_FN_SSI2_SCK,
+ GPIO_FN_SCIF3_TXD,
+ GPIO_FN_HAC_RES,
+ GPIO_FN_SSI2_WS,
+ GPIO_FN_DACK3,
+ GPIO_FN_SDIF0CMD,
+ GPIO_FN_DACK2,
+ GPIO_FN_SDIF0CD,
+ GPIO_FN_DREQ3,
+ GPIO_FN_SDIF0WP,
+ GPIO_FN_SCIF0_CTS,
+ GPIO_FN_DREQ2,
+ GPIO_FN_SDIF0CLK,
+ GPIO_FN_SCIF0_RTS,
+ GPIO_FN_IRL7,
+ GPIO_FN_SDIF0D3,
+ GPIO_FN_SCIF0_SCK,
+ GPIO_FN_IRL6,
+ GPIO_FN_SDIF0D2,
+ GPIO_FN_SCIF0_RXD,
+ GPIO_FN_IRL5,
+ GPIO_FN_SDIF0D1,
+ GPIO_FN_SCIF0_TXD,
+ GPIO_FN_IRL4,
+ GPIO_FN_SDIF0D0,
+ GPIO_FN_SCIF5_SCK,
+ GPIO_FN_FRB,
+ GPIO_FN_SCIF5_RXD,
+ GPIO_FN_IOIS16,
+ GPIO_FN_SCIF5_TXD,
+ GPIO_FN_CE2B,
+ GPIO_FN_DRAK3,
+ GPIO_FN_CE2A,
+ GPIO_FN_SCIF4_SCK,
+ GPIO_FN_DRAK2,
+ GPIO_FN_SSI3_WS,
+ GPIO_FN_SCIF4_RXD,
+ GPIO_FN_DRAK1,
+ GPIO_FN_SSI3_SDATA,
+ GPIO_FN_FSTATUS,
+ GPIO_FN_SCIF4_TXD,
+ GPIO_FN_DRAK0,
+ GPIO_FN_SSI3_SCK,
+ GPIO_FN_FSE,
+};
+
+#endif /* __CPU_SH7786_H__ */