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| author | Ingo Molnar <mingo@elte.hu> | 2009-01-02 22:41:36 +0100 |
|---|---|---|
| committer | Ingo Molnar <mingo@elte.hu> | 2009-01-02 22:41:36 +0100 |
| commit | 923a789b49c7269a0245d5af6afe486188d940df (patch) | |
| tree | c3f168427372e64f7467a794f313416da5086ba0 /arch/sparc/kernel/itlb_miss.S | |
| parent | 103ceffb9501531f6931df6aebc11a05189201f0 (diff) | |
| parent | b840d79631c882786925303c2b0f4fefc31845ed (diff) | |
Merge branch 'linus' into x86/cleanups
Conflicts:
arch/x86/kernel/reboot.c
Diffstat (limited to 'arch/sparc/kernel/itlb_miss.S')
| -rw-r--r-- | arch/sparc/kernel/itlb_miss.S | 39 |
1 files changed, 39 insertions, 0 deletions
diff --git a/arch/sparc/kernel/itlb_miss.S b/arch/sparc/kernel/itlb_miss.S new file mode 100644 index 00000000000..5a8377b5495 --- /dev/null +++ b/arch/sparc/kernel/itlb_miss.S @@ -0,0 +1,39 @@ +/* ITLB ** ICACHE line 1: Context 0 check and TSB load */ + ldxa [%g0] ASI_IMMU_TSB_8KB_PTR, %g1 ! Get TSB 8K pointer + ldxa [%g0] ASI_IMMU, %g6 ! Get TAG TARGET + srlx %g6, 48, %g5 ! Get context + sllx %g6, 22, %g6 ! Zero out context + brz,pn %g5, kvmap_itlb ! Context 0 processing + srlx %g6, 22, %g6 ! Delay slot + TSB_LOAD_QUAD(%g1, %g4) ! Load TSB entry + cmp %g4, %g6 ! Compare TAG + +/* ITLB ** ICACHE line 2: TSB compare and TLB load */ + bne,pn %xcc, tsb_miss_itlb ! Miss + mov FAULT_CODE_ITLB, %g3 + sethi %hi(_PAGE_EXEC_4U), %g4 + andcc %g5, %g4, %g0 ! Executable? + be,pn %xcc, tsb_do_fault + nop ! Delay slot, fill me + stxa %g5, [%g0] ASI_ITLB_DATA_IN ! Load TLB + retry ! Trap done + +/* ITLB ** ICACHE line 3: */ + nop + nop + nop + nop + nop + nop + nop + nop + +/* ITLB ** ICACHE line 4: */ + nop + nop + nop + nop + nop + nop + nop + nop |