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authorLinus Torvalds <torvalds@linux-foundation.org>2008-12-30 17:23:31 -0800
committerLinus Torvalds <torvalds@linux-foundation.org>2008-12-30 17:23:31 -0800
commit6de71484cf9561edb45224f659a9db38b6056d5e (patch)
tree588fe6f7c98147b805085503c863d371e2fa497e /arch/sparc/kernel/itlb_miss.S
parent1dff81f20cd55ffa5a8ee984da70ce0b99d29606 (diff)
parente3c6d4ee545e427b55882d97d3b663c6411645fe (diff)
Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/sparc-next-2.6
* git://git.kernel.org/pub/scm/linux/kernel/git/davem/sparc-next-2.6: (98 commits) sparc: move select of ARCH_SUPPORTS_MSI sparc: drop SUN_IO sparc: unify sections.h sparc: use .data.init_task section for init_thread_union sparc: fix array overrun check in of_device_64.c sparc: unify module.c sparc64: prepare module_64.c for unification sparc64: use bit neutral Elf symbols sparc: unify module.h sparc: introduce CONFIG_BITS sparc: fix hardirq.h removal fallout sparc64: do not export pus_fs_struct sparc: use sparc64 version of scatterlist.h sparc: Commonize memcmp assembler. sparc: Unify strlen assembler. sparc: Add asm/asm.h sparc: Kill memcmp_32.S code which has been ifdef'd out for centuries. sparc: replace for_each_cpu_mask_nr with for_each_cpu sparc: fix sparse warnings in irq_32.c sparc: add include guards to kernel.h ...
Diffstat (limited to 'arch/sparc/kernel/itlb_miss.S')
-rw-r--r--arch/sparc/kernel/itlb_miss.S39
1 files changed, 39 insertions, 0 deletions
diff --git a/arch/sparc/kernel/itlb_miss.S b/arch/sparc/kernel/itlb_miss.S
new file mode 100644
index 00000000000..5a8377b5495
--- /dev/null
+++ b/arch/sparc/kernel/itlb_miss.S
@@ -0,0 +1,39 @@
+/* ITLB ** ICACHE line 1: Context 0 check and TSB load */
+ ldxa [%g0] ASI_IMMU_TSB_8KB_PTR, %g1 ! Get TSB 8K pointer
+ ldxa [%g0] ASI_IMMU, %g6 ! Get TAG TARGET
+ srlx %g6, 48, %g5 ! Get context
+ sllx %g6, 22, %g6 ! Zero out context
+ brz,pn %g5, kvmap_itlb ! Context 0 processing
+ srlx %g6, 22, %g6 ! Delay slot
+ TSB_LOAD_QUAD(%g1, %g4) ! Load TSB entry
+ cmp %g4, %g6 ! Compare TAG
+
+/* ITLB ** ICACHE line 2: TSB compare and TLB load */
+ bne,pn %xcc, tsb_miss_itlb ! Miss
+ mov FAULT_CODE_ITLB, %g3
+ sethi %hi(_PAGE_EXEC_4U), %g4
+ andcc %g5, %g4, %g0 ! Executable?
+ be,pn %xcc, tsb_do_fault
+ nop ! Delay slot, fill me
+ stxa %g5, [%g0] ASI_ITLB_DATA_IN ! Load TLB
+ retry ! Trap done
+
+/* ITLB ** ICACHE line 3: */
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+
+/* ITLB ** ICACHE line 4: */
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop
+ nop