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authorDavid S. Miller <davem@sunset.davemloft.net>2007-05-09 02:35:27 -0700
committerDavid S. Miller <davem@sunset.davemloft.net>2007-05-09 02:35:27 -0700
commitca3dd88e411648c76e1911a729440e3763ba5049 (patch)
treee874ed0c1e91269aa514a443358d4f3738bcb244 /arch/sparc64/kernel/pci_impl.h
parentde372ecd80a42c4fb485c7232475301a18d05184 (diff)
[SPARC64] PCI: Consolidate PCI access code into pci_common.c
All the sun4u controllers do the same thing to compute the physical I/O address to poke, and we can move the sun4v code into this common location too. This one needs a bit of testing, in particular the Sabre code had some funny stuff that would break up u16 and/or u32 accesses into pieces and I didn't think that was needed any more. If it is we need to find out why and add back code to do it again. Signed-off-by: David S. Miller <davem@davemloft.net>
Diffstat (limited to 'arch/sparc64/kernel/pci_impl.h')
-rw-r--r--arch/sparc64/kernel/pci_impl.h6
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/sparc64/kernel/pci_impl.h b/arch/sparc64/kernel/pci_impl.h
index 8e38023868a..f660c2b685e 100644
--- a/arch/sparc64/kernel/pci_impl.h
+++ b/arch/sparc64/kernel/pci_impl.h
@@ -77,6 +77,9 @@ struct pci_pbm_info {
/* Base of PCI Config space, can be per-PBM or shared. */
unsigned long config_space;
+ /* This will be 12 on PCI-E controllers, 8 elsewhere. */
+ unsigned long config_space_reg_bits;
+
/* State of 66MHz capabilities on this PBM. */
int is_66mhz_capable;
int all_devs_66mhz;
@@ -156,4 +159,7 @@ extern void pci_config_write8(u8 *addr, u8 val);
extern void pci_config_write16(u16 *addr, u16 val);
extern void pci_config_write32(u32 *addr, u32 val);
+extern struct pci_ops sun4u_pci_ops;
+extern struct pci_ops sun4v_pci_ops;
+
#endif /* !(PCI_IMPL_H) */