aboutsummaryrefslogtreecommitdiff
path: root/arch/x86/include/asm/msr-index.h
diff options
context:
space:
mode:
authorAndi Kleen <andi@firstfloor.org>2009-02-12 13:49:35 +0100
committerH. Peter Anvin <hpa@zytor.com>2009-02-24 13:41:00 -0800
commit03195c6b40f2b4db92545921daa7c3a19b4e4c32 (patch)
tree895b6a502a4cfe05e4c667f7eb093b74eecef31c /arch/x86/include/asm/msr-index.h
parentee031c31d6381d004bfd386c2e45821211507499 (diff)
x86, mce, cmci: define MSR names and fields for new CMCI registers
Impact: New register definitions only CMCI means support for raising an interrupt on a corrected machine check event instead of having to poll for it. It's a new feature in Intel Nehalem CPUs available on some machine check banks. For details see the IA32 SDM Vol3a 14.5 Define the registers for it as a preparation for further patches. Signed-off-by: Andi Kleen <ak@linux.intel.com> Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Diffstat (limited to 'arch/x86/include/asm/msr-index.h')
-rw-r--r--arch/x86/include/asm/msr-index.h5
1 files changed, 5 insertions, 0 deletions
diff --git a/arch/x86/include/asm/msr-index.h b/arch/x86/include/asm/msr-index.h
index 358acc59ae0..2dbd2314139 100644
--- a/arch/x86/include/asm/msr-index.h
+++ b/arch/x86/include/asm/msr-index.h
@@ -77,6 +77,11 @@
#define MSR_IA32_MC0_ADDR 0x00000402
#define MSR_IA32_MC0_MISC 0x00000403
+/* These are consecutive and not in the normal 4er MCE bank block */
+#define MSR_IA32_MC0_CTL2 0x00000280
+#define CMCI_EN (1ULL << 30)
+#define CMCI_THRESHOLD_MASK 0xffffULL
+
#define MSR_P6_PERFCTR0 0x000000c1
#define MSR_P6_PERFCTR1 0x000000c2
#define MSR_P6_EVNTSEL0 0x00000186