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authorKe Wei <kewei@marvell.com>2008-05-23 10:23:22 +0200
committerLennert Buytenhek <buytenh@marvell.com>2008-06-22 22:45:01 +0200
commit1219715de70956557b9dedf3ee021a73d4f4ec52 (patch)
tree8d778c742bb7e5a0f087e8f8f88a210da6f0125a /arch/x86/kernel/module_64.c
parentab6d15d50637fc25ee941710b23fed09ceb28db3 (diff)
[ARM] Orion: add a separate BRIDGE_INT_TIMER1_CLR define
Some Feroceon-based SoCs have an MBUS bridge interrupt controller that requires writing a one instead of a zero to clear edge interrupt sources such as timer expiry. This patch adds a new BRIDGE_INT_TIMER1_CLR define, which platform code can set to either ~BRIDGE_INT_TIMER1 (write-zero-to-clear) or BRIDGE_INT_TIMER1 (write-one-to-clear) depending on the platform. Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>
Diffstat (limited to 'arch/x86/kernel/module_64.c')
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