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authorCyrill Gorcunov <gorcunov@gmail.com>2008-08-11 18:34:08 +0400
committerIngo Molnar <mingo@elte.hu>2008-08-11 16:43:09 +0200
commit2ae111cdd8d83ebf9de72e36e68a8c84b6ebbeea (patch)
tree0ca28a5869a172d0c76caa3ad8271524cc0a733b /arch/x86/mach-default/setup.c
parent15dd859cacf312f606f54502d1f66537a1e5c78c (diff)
x86: apic interrupts - move assignments to irqinit_32.c, v2
64bit mode APIC interrupt handlers are set within irqinit_64.c. Lets do tha same for 32bit mode which would help in furter code merging. Signed-off-by: Cyrill Gorcunov <gorcunov@gmail.com> Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch/x86/mach-default/setup.c')
-rw-r--r--arch/x86/mach-default/setup.c15
1 files changed, 0 insertions, 15 deletions
diff --git a/arch/x86/mach-default/setup.c b/arch/x86/mach-default/setup.c
index 3d317836be9..b00f5ad10ca 100644
--- a/arch/x86/mach-default/setup.c
+++ b/arch/x86/mach-default/setup.c
@@ -36,15 +36,6 @@ void __init pre_intr_init_hook(void)
init_ISA_irqs();
}
-/*
- * IRQ2 is cascade interrupt to second interrupt controller
- */
-static struct irqaction irq2 = {
- .handler = no_action,
- .mask = CPU_MASK_NONE,
- .name = "cascade",
-};
-
/**
* intr_init_hook - post gate setup interrupt initialisation
*
@@ -60,12 +51,6 @@ void __init intr_init_hook(void)
if (x86_quirks->arch_intr_init())
return;
}
-#ifdef CONFIG_X86_LOCAL_APIC
- apic_intr_init();
-#endif
-
- if (!acpi_ioapic)
- setup_irq(2, &irq2);
}
/**