diff options
| author | Andi Kleen <ak@suse.de> | 2008-01-30 13:33:52 +0100 |
|---|---|---|
| committer | Ingo Molnar <mingo@elte.hu> | 2008-01-30 13:33:52 +0100 |
| commit | 3c868823413d76bdd80c643603be8ab09dcb4d65 (patch) | |
| tree | b40ef3575608c40243cef41965ee16f807a7da7c /arch/x86/mm/pageattr_64.c | |
| parent | 6ba9b7d8f0fe786954015ce5c0ef1837d5df56b7 (diff) | |
x86: c_p_a() fix: reorder TLB / cache flushes to follow Intel recommendation
Intel recommends to first flush the TLBs and then the caches
on caching attribute changes. c_p_a() previously did it the
other way round. Reorder that.
The procedure is still not fully compliant to the Intel documentation
because Intel recommends a all CPU synchronization step between
the TLB flushes and the cache flushes.
However on all new Intel CPUs this is now meaningless anyways
because they support Self-Snoop and can skip the cache flush
step anyway.
[ mingo@elte.hu: decoupled from clflush and ported it to x86.git ]
Signed-off-by: Andi Kleen <ak@suse.de>
Acked-by: Jan Beulich <jbeulich@novell.com>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Diffstat (limited to 'arch/x86/mm/pageattr_64.c')
| -rw-r--r-- | arch/x86/mm/pageattr_64.c | 3 |
1 files changed, 2 insertions, 1 deletions
diff --git a/arch/x86/mm/pageattr_64.c b/arch/x86/mm/pageattr_64.c index 4d172881af7..3ccdb1401e6 100644 --- a/arch/x86/mm/pageattr_64.c +++ b/arch/x86/mm/pageattr_64.c @@ -82,6 +82,8 @@ static void flush_kernel_map(void *arg) struct list_head *l = (struct list_head *)arg; struct page *pg; + __flush_tlb_all(); + /* When clflush is available always use it because it is much cheaper than WBINVD. */ /* clflush is still broken. Disable for now. */ @@ -94,7 +96,6 @@ static void flush_kernel_map(void *arg) clflush_cache_range(addr, PAGE_SIZE); } } - __flush_tlb_all(); } static inline void flush_map(struct list_head *l) |