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authorAndi Kleen <ak@linux.intel.com>2009-04-27 18:42:48 +0200
committerH. Peter Anvin <hpa@zytor.com>2009-05-28 09:24:12 -0700
commit2e6f694fde0a7158590e121962ca2e3c06633528 (patch)
treef81d898720ddacfe247253747f8579b075b3f8d4 /arch/x86
parent06b7a7a5ec917761969444fee967c43868a76468 (diff)
x86, mce: port K7 bank 0 quirk to 64bit mce code
Various K7 have broken bank 0s. Don't enable it by default Port from the 32bit code. Signed-off-by: Andi Kleen <ak@linux.intel.com> Signed-off-by: H. Peter Anvin <hpa@zytor.com> Signed-off-by: Hidetoshi Seto <seto.hidetoshi@jp.fujitsu.com> Signed-off-by: H. Peter Anvin <hpa@zytor.com>
Diffstat (limited to 'arch/x86')
-rw-r--r--arch/x86/kernel/cpu/mcheck/mce.c6
1 files changed, 6 insertions, 0 deletions
diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c
index 1dcd3be0332..1336280edcc 100644
--- a/arch/x86/kernel/cpu/mcheck/mce.c
+++ b/arch/x86/kernel/cpu/mcheck/mce.c
@@ -650,6 +650,12 @@ static void mce_cpu_quirks(struct cpuinfo_x86 *c)
*/
mce_bootlog = 0;
}
+ /*
+ * Various K7s with broken bank 0 around. Always disable
+ * by default.
+ */
+ if (c->x86 == 6)
+ bank[0] = 0;
}
if (c->x86_vendor == X86_VENDOR_INTEL) {