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authorPeter Zijlstra <a.p.zijlstra@chello.nl>2010-02-10 16:10:48 +0100
committerIngo Molnar <mingo@elte.hu>2010-02-26 10:56:54 +0100
commit6667661df4bc76083edf1e08831c20f64429709d (patch)
tree0fdae0f6209df3e1756f34b371ce9f0f7493f011 /arch/x86
parent6e37738a2fac964583debe91099bc3248554f6e5 (diff)
perf_events, x86: Remove superflous MSR writes
We re-program the event control register every time we reset the count, this appears to be superflous, hence remove it. Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl> Cc: Arjan van de Ven <arjan@linux.intel.com> LKML-Reference: <new-submission> Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch/x86')
-rw-r--r--arch/x86/kernel/cpu/perf_event.c3
1 files changed, 0 insertions, 3 deletions
diff --git a/arch/x86/kernel/cpu/perf_event.c b/arch/x86/kernel/cpu/perf_event.c
index ad096562d69..dd09ccc867d 100644
--- a/arch/x86/kernel/cpu/perf_event.c
+++ b/arch/x86/kernel/cpu/perf_event.c
@@ -2009,9 +2009,6 @@ static int intel_pmu_save_and_restart(struct perf_event *event)
x86_perf_event_update(event, hwc, idx);
ret = x86_perf_event_set_period(event, hwc, idx);
- if (event->state == PERF_EVENT_STATE_ACTIVE)
- intel_pmu_enable_event(hwc, idx);
-
return ret;
}