diff options
| author | Paul Walmsley <paul@pwsan.com> | 2009-02-05 20:45:28 -0700 |
|---|---|---|
| committer | Russell King <rmk+kernel@arm.linux.org.uk> | 2009-02-23 14:52:51 +0000 |
| commit | 7eb1afc9765d07c9036b1ad9e7c03e5bd1a58a2b (patch) | |
| tree | 481467823b3810af2a94597129748aaf04f902d2 /arch | |
| parent | d41ad52040dee5043ce6b1d49a1c8864706d2bfd (diff) | |
[ARM] OMAP3 powerdomains: make USBTLL SAR only available on ES3.1 and beyond
Richard Woodruff writes that chip errata prevent USBTLL SAR from working
on OMAP3 ES levels before ES3.1:
http://marc.info/?l=linux-arm-kernel&m=123319614808833&w=2
Update the OMAP3 powerdomain structures appropriately.
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Cc: Richard Woodruff <r-woodruff2@ti.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/arm/mach-omap2/powerdomains.h | 3 | ||||
| -rw-r--r-- | arch/arm/mach-omap2/powerdomains34xx.h | 25 |
2 files changed, 25 insertions, 3 deletions
diff --git a/arch/arm/mach-omap2/powerdomains.h b/arch/arm/mach-omap2/powerdomains.h index 1329443f2cd..691470ea4c6 100644 --- a/arch/arm/mach-omap2/powerdomains.h +++ b/arch/arm/mach-omap2/powerdomains.h @@ -171,7 +171,8 @@ static struct powerdomain *powerdomains_omap[] __initdata = { &iva2_pwrdm, &mpu_34xx_pwrdm, &neon_pwrdm, - &core_34xx_pwrdm, + &core_34xx_pre_es3_1_pwrdm, + &core_34xx_es3_1_pwrdm, &cam_pwrdm, &dss_pwrdm, &per_pwrdm, diff --git a/arch/arm/mach-omap2/powerdomains34xx.h b/arch/arm/mach-omap2/powerdomains34xx.h index 78acfce8bbd..4dcf94b800a 100644 --- a/arch/arm/mach-omap2/powerdomains34xx.h +++ b/arch/arm/mach-omap2/powerdomains34xx.h @@ -200,12 +200,33 @@ static struct powerdomain mpu_34xx_pwrdm = { }; /* No wkdeps or sleepdeps for 34xx core apparently */ -static struct powerdomain core_34xx_pwrdm = { +static struct powerdomain core_34xx_pre_es3_1_pwrdm = { .name = "core_pwrdm", .prcm_offs = CORE_MOD, - .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430), + .omap_chip = OMAP_CHIP_INIT(CHIP_IS_OMAP3430ES1 | + CHIP_IS_OMAP3430ES2 | + CHIP_IS_OMAP3430ES3_0), + .pwrsts = PWRSTS_OFF_RET_ON, + .dep_bit = OMAP3430_EN_CORE_SHIFT, + .banks = 2, + .pwrsts_mem_ret = { + [0] = PWRSTS_OFF_RET, /* MEM1RETSTATE */ + [1] = PWRSTS_OFF_RET, /* MEM2RETSTATE */ + }, + .pwrsts_mem_on = { + [0] = PWRSTS_OFF_RET_ON, /* MEM1ONSTATE */ + [1] = PWRSTS_OFF_RET_ON, /* MEM2ONSTATE */ + }, +}; + +/* No wkdeps or sleepdeps for 34xx core apparently */ +static struct powerdomain core_34xx_es3_1_pwrdm = { + .name = "core_pwrdm", + .prcm_offs = CORE_MOD, + .omap_chip = OMAP_CHIP_INIT(CHIP_GE_OMAP3430ES3_1), .pwrsts = PWRSTS_OFF_RET_ON, .dep_bit = OMAP3430_EN_CORE_SHIFT, + .flags = PWRDM_HAS_HDWR_SAR, /* for USBTLL only */ .banks = 2, .pwrsts_mem_ret = { [0] = PWRSTS_OFF_RET, /* MEM1RETSTATE */ |