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authorThomas Gleixner <tglx@linutronix.de>2008-12-09 21:43:39 +0100
committerIngo Molnar <mingo@elte.hu>2008-12-11 15:45:45 +0100
commit4ac13294e44664bb7edf4daf52edb71e7c6bbe84 (patch)
treeaccb533350a655e39a8ab846abc37018b2f87ccf /arch
parent43874d238d5f208854a73c3225ca2a22833eec8b (diff)
perf counters: protect them against CSTATE transitions
Impact: fix rare lost events problem There are CPUs whose performance counters misbehave on CSTATE transitions, so provide a way to just disable/enable them around deep idle methods. (hw_perf_enable_all() is cheap on x86.) Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Signed-off-by: Ingo Molnar <mingo@elte.hu>
Diffstat (limited to 'arch')
-rw-r--r--arch/x86/kernel/cpu/perf_counter.c14
1 files changed, 13 insertions, 1 deletions
diff --git a/arch/x86/kernel/cpu/perf_counter.c b/arch/x86/kernel/cpu/perf_counter.c
index 6a93d1f04d9..0a7f3bea2dc 100644
--- a/arch/x86/kernel/cpu/perf_counter.c
+++ b/arch/x86/kernel/cpu/perf_counter.c
@@ -12,6 +12,7 @@
#include <linux/notifier.h>
#include <linux/hardirq.h>
#include <linux/kprobes.h>
+#include <linux/module.h>
#include <linux/kdebug.h>
#include <linux/sched.h>
@@ -119,10 +120,21 @@ void hw_perf_enable_all(void)
wrmsr(MSR_CORE_PERF_GLOBAL_CTRL, perf_counter_mask, 0);
}
-void hw_perf_disable_all(void)
+void hw_perf_restore_ctrl(u64 ctrl)
{
+ wrmsr(MSR_CORE_PERF_GLOBAL_CTRL, ctrl, 0);
+}
+EXPORT_SYMBOL_GPL(hw_perf_restore_ctrl);
+
+u64 hw_perf_disable_all(void)
+{
+ u64 ctrl;
+
+ rdmsrl(MSR_CORE_PERF_GLOBAL_CTRL, ctrl);
wrmsr(MSR_CORE_PERF_GLOBAL_CTRL, 0, 0);
+ return ctrl;
}
+EXPORT_SYMBOL_GPL(hw_perf_disable_all);
static inline void
__hw_perf_counter_disable(struct hw_perf_counter *hwc, unsigned int idx)