diff options
| author | Ralf Baechle <ralf@linux-mips.org> | 2006-03-14 23:52:47 +0000 |
|---|---|---|
| committer | Ralf Baechle <ralf@linux-mips.org> | 2006-03-18 16:59:30 +0000 |
| commit | 4308cb16286c96d980570cc5319173b524220c06 (patch) | |
| tree | 89ffe22e6fd71d320b51ce8817a11cdaba3ae503 /arch | |
| parent | a77f124294822203660b0926392b963cfa72fcf4 (diff) | |
[MIPS] Sibyte: Fix interrupt timer off by one bug.
From Dave Johnson <djohnson+linuxmips@sw.starentnetworks.com>:
The timers need to be loaded with 1 less than the desired interval not
the interval itself.
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
Diffstat (limited to 'arch')
| -rw-r--r-- | arch/mips/sibyte/sb1250/time.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/arch/mips/sibyte/sb1250/time.c b/arch/mips/sibyte/sb1250/time.c index 511c89d65f3..adc0b5271a0 100644 --- a/arch/mips/sibyte/sb1250/time.c +++ b/arch/mips/sibyte/sb1250/time.c @@ -75,10 +75,10 @@ void sb1250_time_init(void) /* Disable the timer and set up the count */ __raw_writeq(0, IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_CFG))); #ifdef CONFIG_SIMULATION - __raw_writeq(50000 / HZ, + __raw_writeq((50000 / HZ) - 1, IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT))); #else - __raw_writeq(1000000 / HZ, + __raw_writeq((V_SCD_TIMER_FREQ / HZ) - 1, IOADDR(A_SCD_TIMER_REGISTER(cpu, R_SCD_TIMER_INIT))); #endif |