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authorLin Ming <ming.m.lin@intel.com>2009-03-19 09:51:01 +0800
committerLen Brown <len.brown@intel.com>2009-03-27 12:11:03 -0400
commitc3dd25f4c1ca84baa170c0a3a15a884f4f06297e (patch)
tree817cc0715dcc8e4d546cee10fce6d2d09553e80f /drivers/acpi/acpica
parentf9ca058430333c9a24c5ca926aa445125f88df18 (diff)
ACPICA: Clear PM register write-only bits on reading
Affects PM1 Control register only. When reading the register, zero the write-only bits as per the ACPI spec. ACPICA BZ 443. Lin Ming. http://www.acpica.org/bugzilla/show_bug.cgi?id=443 Signed-off-by: Lin Ming <ming.m.lin@intel.com> Signed-off-by: Bob Moore <robert.moore@intel.com> Signed-off-by: Len Brown <len.brown@intel.com>
Diffstat (limited to 'drivers/acpi/acpica')
-rw-r--r--drivers/acpi/acpica/aclocal.h4
-rw-r--r--drivers/acpi/acpica/hwregs.c7
2 files changed, 11 insertions, 0 deletions
diff --git a/drivers/acpi/acpica/aclocal.h b/drivers/acpi/acpica/aclocal.h
index 42ef0cbf70f..772ee5c4ccc 100644
--- a/drivers/acpi/acpica/aclocal.h
+++ b/drivers/acpi/acpica/aclocal.h
@@ -781,6 +781,10 @@ struct acpi_bit_register_info {
*/
#define ACPI_PM1_STATUS_PRESERVED_BITS 0x0800 /* Bit 11 */
+/* Write-only bits must be zeroed by software */
+
+#define ACPI_PM1_CONTROL_WRITEONLY_BITS 0x2004 /* Bits 13, 2 */
+
/* For control registers, both ignored and reserved bits must be preserved */
#define ACPI_PM1_CONTROL_IGNORED_BITS 0x0201 /* Bits 9, 0(SCI_EN) */
diff --git a/drivers/acpi/acpica/hwregs.c b/drivers/acpi/acpica/hwregs.c
index f8ee0a7fd44..7b2fb602b5c 100644
--- a/drivers/acpi/acpica/hwregs.c
+++ b/drivers/acpi/acpica/hwregs.c
@@ -207,6 +207,13 @@ acpi_hw_register_read(u32 register_id, u32 * return_value)
xpm1a_control_block,
&acpi_gbl_FADT.
xpm1b_control_block);
+
+ /*
+ * Zero the write-only bits. From the ACPI specification, "Hardware
+ * Write-Only Bits": "Upon reads to registers with write-only bits,
+ * software masks out all write-only bits."
+ */
+ value &= ~ACPI_PM1_CONTROL_WRITEONLY_BITS;
break;
case ACPI_REGISTER_PM2_CONTROL: /* 8-bit access */