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authorMa Ling <ling.ma@intel.com>2009-03-18 20:13:23 +0800
committerEric Anholt <eric@anholt.net>2009-03-27 14:45:11 -0700
commit044c7c415a68077b7c444c753aa03a35149e881a (patch)
treec8da161ad9f396773d05028b9e63e0faa62d701b /drivers/gpu/Makefile
parent568d9a8f6d4bf81e0672c74573dc02981d31e3ea (diff)
drm/i915: Use documented PLL timing limits for G4X platform
The values come from the internal reference spreadsheet on PLL timing limits for the G4X chipsets. Part of fixing fd.o bug #17508 Signed-off-by: Ma Ling <ling.ma@intel.com> [anholt: Cleaned up some whitespace] Signed-off-by: Eric Anholt <eric@anholt.net>
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