diff options
| author | Eric Anholt <eric@anholt.net> | 2008-10-15 00:05:58 -0700 |
|---|---|---|
| committer | Dave Airlie <airlied@linux.ie> | 2008-10-18 07:10:53 +1000 |
| commit | b612eda98e4b4bae4c98a863f039bc89425f9039 (patch) | |
| tree | 176a9db19d8b9e1862b2c6f148a7a8932ebb1c3c /drivers/gpu/drm/i915/i915_gem_tiling.c | |
| parent | 6dbe2772d6af067845bab57be490c302f4490ac7 (diff) | |
i915: GM45 has GM965-style MCH setup.
Fixes tiling swizzling mode failures that manifest in glReadPixels().
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/i915/i915_gem_tiling.c')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_gem_tiling.c | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/drivers/gpu/drm/i915/i915_gem_tiling.c b/drivers/gpu/drm/i915/i915_gem_tiling.c index 6b3f1e4a34a..e8b85ac4ca0 100644 --- a/drivers/gpu/drm/i915/i915_gem_tiling.c +++ b/drivers/gpu/drm/i915/i915_gem_tiling.c @@ -96,7 +96,8 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev) */ swizzle_x = I915_BIT_6_SWIZZLE_NONE; swizzle_y = I915_BIT_6_SWIZZLE_NONE; - } else if ((!IS_I965G(dev) && !IS_G33(dev)) || IS_I965GM(dev)) { + } else if ((!IS_I965G(dev) && !IS_G33(dev)) || IS_I965GM(dev) || + IS_GM45(dev)) { uint32_t dcc; /* On 915-945 and GM965, channel interleave by the CPU is @@ -118,7 +119,7 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev) dcc & DCC_CHANNEL_XOR_DISABLE) { swizzle_x = I915_BIT_6_SWIZZLE_9_10; swizzle_y = I915_BIT_6_SWIZZLE_9; - } else if (IS_I965GM(dev)) { + } else if (IS_I965GM(dev) || IS_GM45(dev)) { /* GM965 only does bit 11-based channel * randomization */ |