diff options
| author | Linus Torvalds <torvalds@linux-foundation.org> | 2010-03-24 16:42:43 -0700 |
|---|---|---|
| committer | Linus Torvalds <torvalds@linux-foundation.org> | 2010-03-24 16:42:43 -0700 |
| commit | 6467a71c56934251f3c917bd4386387c2a97b41e (patch) | |
| tree | 09f930fda8c6c555d488971d76e728846be55650 /drivers/gpu/drm/i915/i915_reg.h | |
| parent | 18020a0d8cccad0d3642219d6aef789420c04c1f (diff) | |
| parent | 6e6c822868f113dabe3c33bdd91e883cc28fa11b (diff) | |
Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/anholt/drm-intel
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/anholt/drm-intel:
drm/i915: Stop trying to use ACPI lid status to determine LVDS connection.
drm/intel: fix up set_tiling for untiled->tiled transition
drm/i915: Set up the documented clock gating on Sandybridge and Ironlake.
agp/intel: Don't do the chipset flush on Sandybridge.
agp/intel: Respect the GTT size on Sandybridge for scratch page setup.
drm/i915: fix small leak on overlay error path
drm/i915: Avoid NULL deref in get_pages() unwind after error.
drm/i915: Fix check with IS_GEN6
drivers/gpu/drm/i915/intel_bios.c: fix continuation line formats
drm/i915: Enable VS timer dispatch.
drm/i915: Rename FBC_C3_IDLE to FBC_CTL_C3_IDLE to match other registers
drm/i915: remove an unnecessary wait_request()
drm/i915: Don't bother with the BKL for GEM ioctls.
Diffstat (limited to 'drivers/gpu/drm/i915/i915_reg.h')
| -rw-r--r-- | drivers/gpu/drm/i915/i915_reg.h | 14 |
1 files changed, 13 insertions, 1 deletions
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 3d59862c7cc..cbbf59f56df 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -298,6 +298,10 @@ #define INSTDONE 0x02090 #define NOPID 0x02094 #define HWSTAM 0x02098 + +#define MI_MODE 0x0209c +# define VS_TIMER_DISPATCH (1 << 6) + #define SCPD0 0x0209c /* 915+ only */ #define IER 0x020a0 #define IIR 0x020a4 @@ -366,7 +370,7 @@ #define FBC_CTL_PERIODIC (1<<30) #define FBC_CTL_INTERVAL_SHIFT (16) #define FBC_CTL_UNCOMPRESSIBLE (1<<14) -#define FBC_C3_IDLE (1<<13) +#define FBC_CTL_C3_IDLE (1<<13) #define FBC_CTL_STRIDE_SHIFT (5) #define FBC_CTL_FENCENO (1<<0) #define FBC_COMMAND 0x0320c @@ -2172,6 +2176,14 @@ #define DISPLAY_PORT_PLL_BIOS_1 0x46010 #define DISPLAY_PORT_PLL_BIOS_2 0x46014 +#define PCH_DSPCLK_GATE_D 0x42020 +# define DPFDUNIT_CLOCK_GATE_DISABLE (1 << 7) +# define DPARBUNIT_CLOCK_GATE_DISABLE (1 << 5) + +#define PCH_3DCGDIS0 0x46020 +# define MARIUNIT_CLOCK_GATE_DISABLE (1 << 18) +# define SVSMUNIT_CLOCK_GATE_DISABLE (1 << 1) + #define FDI_PLL_FREQ_CTL 0x46030 #define FDI_PLL_FREQ_CHANGE_REQUEST (1<<24) #define FDI_PLL_FREQ_LOCK_LIMIT_MASK 0xfff00 |