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authorDave Airlie <airlied@redhat.com>2010-01-11 14:42:58 +1000
committerDave Airlie <airlied@redhat.com>2010-01-11 14:42:58 +1000
commit0c9d2c418aa4a45534943c4c9a1c8dda82d3b481 (patch)
tree7844c421b7bd20b9b4e9c17b425ee050653eb407 /drivers/gpu/drm/radeon/r300.c
parent94fd163d86b049842856864cdeac318131ec576d (diff)
parent804c7559e9376c3ba78ae15a30337b1e24f8ae80 (diff)
Merge remote branch 'korg/drm-radeon-next' into drm-linus
* korg/drm-radeon-next: drm/radeon/kms: add additional safe regs for r4xx/rs6xx and r5xx drm/radeon/kms: Don't try to enable IRQ if we have no handler installed drm: Avoid calling vblank function is vblank wasn't initialized drm/radeon: mkregtable.c: close a file before exit drm/radeon/kms: Make sure we release AGP device if we acquired it drm/radeon/kms: Schedule host path read cache flush through the ring V2 drm/radeon/kms: Workaround RV410/R420 CP errata (V3) drm/radeon/kms: detect sideport memory on IGP chips drm/radeon: fix a couple of array index errors drm/radeon/kms: add support for eDP (embedded DisplayPort) drm: Add eDP connector type drm/radeon/kms: pull in the latest upstream ObjectID.h changes drm/radeon/kms: whitespace changes to ObjectID.h drm/radeon/kms: fix typo in atom connector type handling
Diffstat (limited to 'drivers/gpu/drm/radeon/r300.c')
-rw-r--r--drivers/gpu/drm/radeon/r300.c17
1 files changed, 16 insertions, 1 deletions
diff --git a/drivers/gpu/drm/radeon/r300.c b/drivers/gpu/drm/radeon/r300.c
index 3f2cc9e2e8d..0051d11b907 100644
--- a/drivers/gpu/drm/radeon/r300.c
+++ b/drivers/gpu/drm/radeon/r300.c
@@ -36,7 +36,15 @@
#include "rv350d.h"
#include "r300_reg_safe.h"
-/* This files gather functions specifics to: r300,r350,rv350,rv370,rv380 */
+/* This files gather functions specifics to: r300,r350,rv350,rv370,rv380
+ *
+ * GPU Errata:
+ * - HOST_PATH_CNTL: r300 family seems to dislike write to HOST_PATH_CNTL
+ * using MMIO to flush host path read cache, this lead to HARDLOCKUP.
+ * However, scheduling such write to the ring seems harmless, i suspect
+ * the CP read collide with the flush somehow, or maybe the MC, hard to
+ * tell. (Jerome Glisse)
+ */
/*
* rv370,rv380 PCIE GART
@@ -178,6 +186,11 @@ void r300_fence_ring_emit(struct radeon_device *rdev,
/* Wait until IDLE & CLEAN */
radeon_ring_write(rdev, PACKET0(0x1720, 0));
radeon_ring_write(rdev, (1 << 17) | (1 << 16) | (1 << 9));
+ radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
+ radeon_ring_write(rdev, rdev->config.r300.hdp_cntl |
+ RADEON_HDP_READ_BUFFER_INVALIDATE);
+ radeon_ring_write(rdev, PACKET0(RADEON_HOST_PATH_CNTL, 0));
+ radeon_ring_write(rdev, rdev->config.r300.hdp_cntl);
/* Emit fence sequence & fire IRQ */
radeon_ring_write(rdev, PACKET0(rdev->fence_drv.scratch_reg, 0));
radeon_ring_write(rdev, fence->seq);
@@ -1258,6 +1271,7 @@ static int r300_startup(struct radeon_device *rdev)
}
/* Enable IRQ */
r100_irq_set(rdev);
+ rdev->config.r300.hdp_cntl = RREG32(RADEON_HOST_PATH_CNTL);
/* 1M ring buffer */
r = r100_cp_init(rdev, 1024 * 1024);
if (r) {
@@ -1322,6 +1336,7 @@ void r300_fini(struct radeon_device *rdev)
rv370_pcie_gart_fini(rdev);
if (rdev->flags & RADEON_IS_PCI)
r100_pci_gart_fini(rdev);
+ radeon_agp_fini(rdev);
radeon_irq_kms_fini(rdev);
radeon_fence_driver_fini(rdev);
radeon_bo_fini(rdev);