diff options
| author | Alex Deucher <alexdeucher@gmail.com> | 2009-11-02 16:01:27 -0500 |
|---|---|---|
| committer | Dave Airlie <airlied@redhat.com> | 2009-11-04 09:53:25 +1000 |
| commit | d6f28938d9426d12eea1578949f1d73d24ad37ec (patch) | |
| tree | 5450e0a9c108ec9d5875679ece20faa770c44310 /drivers/gpu/drm/radeon/r600.c | |
| parent | df67bed92fa86ef926da8b62a6da68722388ff72 (diff) | |
drm/radeon/kms: Don't RMW CP_RB_CNTL
Immediate readback seems faulty on some chips. I
suspect it takes a while to get through the fifo
to the actual register backbone. There's no need
to read it back, so, just write the driver's copy
of the register's value directly.
Should fix bug 24535 and possibly 24218
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Diffstat (limited to 'drivers/gpu/drm/radeon/r600.c')
| -rw-r--r-- | drivers/gpu/drm/radeon/r600.c | 8 |
1 files changed, 3 insertions, 5 deletions
diff --git a/drivers/gpu/drm/radeon/r600.c b/drivers/gpu/drm/radeon/r600.c index e87475c87d5..60fbb236edf 100644 --- a/drivers/gpu/drm/radeon/r600.c +++ b/drivers/gpu/drm/radeon/r600.c @@ -1272,19 +1272,17 @@ int r600_cp_resume(struct radeon_device *rdev) /* Set ring buffer size */ rb_bufsz = drm_order(rdev->cp.ring_size / 8); + tmp = RB_NO_UPDATE | (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz; #ifdef __BIG_ENDIAN - WREG32(CP_RB_CNTL, BUF_SWAP_32BIT | RB_NO_UPDATE | - (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz); -#else - WREG32(CP_RB_CNTL, RB_NO_UPDATE | (drm_order(RADEON_GPU_PAGE_SIZE/8) << 8) | rb_bufsz); + tmp |= BUF_SWAP_32BIT; #endif + WREG32(CP_RB_CNTL, tmp); WREG32(CP_SEM_WAIT_TIMER, 0x4); /* Set the write pointer delay */ WREG32(CP_RB_WPTR_DELAY, 0); /* Initialize the ring buffer's read and write pointers */ - tmp = RREG32(CP_RB_CNTL); WREG32(CP_RB_CNTL, tmp | RB_RPTR_WR_ENA); WREG32(CP_RB_RPTR_WR, 0); WREG32(CP_RB_WPTR, 0); |