diff options
| author | Alex Deucher <alexdeucher@gmail.com> | 2009-09-25 18:33:08 -0400 |
|---|---|---|
| committer | Dave Airlie <airlied@linux.ie> | 2009-09-26 09:09:50 +1000 |
| commit | 210bed8f827471e271f894fb99ee879a5d27cf30 (patch) | |
| tree | 48310ed350bde481c6238c5a7de2bbe317be6f9e /drivers/gpu | |
| parent | 2b5d6c538b48772ba3351b8a8eed096f7af8de5d (diff) | |
drm/radeon/r600: fix offset handling in CS parser
Need add reloc offset to the offset in the actual
packet. Fixes use of the DRAW_INDEX packet by the 3D
driver.
[airlied: modified first one where idx_value == ib[idx+0]
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@linux.ie>
Diffstat (limited to 'drivers/gpu')
| -rw-r--r-- | drivers/gpu/drm/radeon/r600_cs.c | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/drivers/gpu/drm/radeon/r600_cs.c b/drivers/gpu/drm/radeon/r600_cs.c index 20eb66dbb3a..ac7d93e2d5d 100644 --- a/drivers/gpu/drm/radeon/r600_cs.c +++ b/drivers/gpu/drm/radeon/r600_cs.c @@ -380,7 +380,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p, return -EINVAL; } ib[idx+0] = idx_value + (u32)(reloc->lobj.gpu_offset & 0xffffffff); - ib[idx+1] = upper_32_bits(reloc->lobj.gpu_offset) & 0xff; + ib[idx+1] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff; break; case PACKET3_DRAW_INDEX_AUTO: if (pkt->count != 1) { @@ -408,7 +408,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p, return -EINVAL; } ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff); - ib[idx+2] = upper_32_bits(reloc->lobj.gpu_offset) & 0xff; + ib[idx+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff; } break; case PACKET3_SURFACE_SYNC: @@ -439,7 +439,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p, return -EINVAL; } ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff); - ib[idx+2] |= upper_32_bits(reloc->lobj.gpu_offset) & 0xff; + ib[idx+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff; } break; case PACKET3_EVENT_WRITE_EOP: @@ -453,7 +453,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p, return -EINVAL; } ib[idx+1] += (u32)(reloc->lobj.gpu_offset & 0xffffffff); - ib[idx+2] |= upper_32_bits(reloc->lobj.gpu_offset) & 0xff; + ib[idx+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff; break; case PACKET3_SET_CONFIG_REG: start_reg = (idx_value << 2) + PACKET3_SET_CONFIG_REG_OFFSET; @@ -575,7 +575,7 @@ static int r600_packet3_check(struct radeon_cs_parser *p, return -EINVAL; } ib[idx+1+(i*7)+0] += (u32)((reloc->lobj.gpu_offset) & 0xffffffff); - ib[idx+1+(i*7)+2] |= upper_32_bits(reloc->lobj.gpu_offset) & 0xff; + ib[idx+1+(i*7)+2] += upper_32_bits(reloc->lobj.gpu_offset) & 0xff; break; case SQ_TEX_VTX_INVALID_TEXTURE: case SQ_TEX_VTX_INVALID_BUFFER: |